Phase-locked loops in an IC-based clock distribution system - Embedded.com

Phase-locked loops in an IC-based clock distribution system

Timing signals are essential to the reliable operation of digital equipment, communication systems, and networks to coordinate actions of circuits. These signals synchronize the flow of data signals among synchronous paths. They also control the command signals sent out to govern interconnected digital blocks.

A simple approach to generating such a signal is to have a local oscillator, often referred as the clock. However, many of today’s complex systems require a variety of clock frequencies with high precision and low noise. A system designer may have to put as many oscillators as the different frequencies required on the system. This practice consumes board space and increases complexity and system cost.

Figure 1: Representation of multiple crystal oscillators and flexible clock synthesizer

One approach to this problem is to use a PLL-based (phase-locked loop) clock distribution method. A PLL can be integrated into a single IC to fan out multiple clocks of different frequencies, as shown in Figure 1 . Such a silicon IC can be designed with a significantly smaller size and lower power consumption than multiple oscillators.

PLLs are widely used to generate on-chip clocks in high-performance digital systems. In addition, PLLs are incorporated into almost every large-scale mixed-signal and digital system-on-chip (SoC). A PLL-based clock distribution system can take any single board level clock source as input and generate multiple clock outputs with a frequency that is lower or greater compared to the input source.

The other hidden beauty of such a distribution system is that all the output clocks can be made to have a fixed phase relationship to each other. This feature is useful in systems where it is required to deliver varying frequency signals to different digital blocks while keeping their operation in sync.

There are several common applications of PLL in clock distribution:

  • Noise and jitter reduction
  • Zero delay buffer
  • Clock de-skew application
  • Frequency synthesis
  • Spread spectrum clock
  • Clock and data recovery

This article covers the basics of PLLs, including their architecture, working principles, jitter in clock, clock stability, phase noise, applications, and practical examples of PLL in use.

Basics of PLL
A basic PLL is a negative feedback system that receives an incoming oscillating signal and generates an output waveform that exerts the same phase/frequency relationship as the input signal. This is achieved by constantly comparing the phase of output signal to the input signal with a phase/frequency detector (PFD).

Figure 2: Block diagram of a PLL

As shown in Figure 2 , a PLL is comprised of a phase/frequency detector (PFD), charge pump (CP), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO). An input reference frequency (FREF) is sent to one of the PFD inputs. The other input terminal of PFD is driven by a divided version of VCO output signal to provide a negative feedback to the loop. The PFD detects differences in phase and frequency between the reference and feedback inputs to generate compensating up (UP) or down (DN) signals.

If reference input (FREF) occurs before that of feedback input (FBK), indicating that the VCO is running too slowly, the PFD produces a UP signal that lasts until the rising edge of the FBK. If the FBK occurs before FREF, the PFD produces a DN signal that is triggered on the rising edge of the FBK input and lasts until the rising edge of FREF. If the FBK frequency is less than that of FREF, the pulse-width of the UP signal is greater than the width of DN signal and vice versa. In this way, the PFD produces control signals that are unique for any phase and frequency relationship between reference and feedback signal.

These control signals are then passed through CP and a loop filter to generate a control voltage (Vctrl), which feeds into a VCO, the frequency of which is dependent on the control voltage input. Thus, based on phase/frequency relationship of input and feedback signal, the VCO can be forced to run faster or slower, which finally locks to oscillate at a fixed frequency once two inputs at PFD are phase/frequency aligned. The output of the VCO is an internally generated oscillator waveform. At steady state, the PLL system frequency is:

FPLL = FVCO = FREF * P

Where:
FPLL = PLL frequency
FREF = Reference frequency
P = Feedback divider

The PLL is designed to operate within a limited band of input frequencies. If FREF is outside the defined band, circuit will not lock, thus FVCO will be different than expected one.

The range of FREF from Fmin to Fmax where the PLL remains in locked condition is called the lock range of the PLL. Out of lock range (i.e., Fmax < Fref < Fmin), the PLL becomes unlocked. When the PLL is unlocked, the VCO oscillates at the frequency Ffr, called the free-running frequency of VCO. The PLL can achieve the lock again if FREF gets close enough to Ffr. This narrow band (△Fc) of frequency, centered at Ffr so that the initially unlocked PLL acquires the lock again, is called the ‘capture range’ of the PLL.

Figure 3: Characteristics of PLL

Phase frequency detector
The integrated function of PFD and CP is to detect a phase and/or frequency error between two input signals and generate an output current whose value averaged over one period of the reference clock is dependent on the input phase/frequency error. Figure 4 shows the block diagram of integrated PFD and CP. The output current (UP and DN) from PFD charges or discharges the loop filter at the next stage, which generates Vctrl to drive VCO. Output of the VCO is then fed back to the PFD to be compared against a reference clock, thereby closing the loop.

Figure 4: Block diagram of PFD combined with CP

Figure 5 shows a logic and timing diagram of a PFD function. It consists of two D-type flip-flops (DFF) with its D-inputs kept high. Assuming these DFFs are positive-edge triggered, a rising edge on the reference clock asserts the UP pulse (DFF1 output), and a rising edge on the feedback clock asserts the DN pulse (DFF2 output). The Q outputs of both DFFs are connected to a two-inputs AND gate. Output of this AND gate is used to reset DFFs after a specified delay when both UP/DN pulses are present. The combined delay of the AND gate and the delay of the ‘Delay cell’ specifies how long both pulses will remain asserted for before they are both reset. This is known as the reset delay; this time is crucial to avoid a DEAD ZONE in the PLL. A dead band is the condition where the charge pump and the PFD provide no correction output for a given phase offset at the PFD inputs.

Figure 5(a): Logic diagram of PFD

Figure 5(b): Timing diagram of PFD

In the timing diagram above it is assumed that FBK leads FREF i.e FBK > FREF, hence DN pulses dominate to reduce the VCO frequency. It can also be easily derived from above logic diagram that when FREF > FBK the UP pulses will dominate to increase VCO frequency.

To understand the dead zone, let’s consider the situation without the delay element in PFD. In this condition both DFFs will be triggered simultaneously and an immediate RESET pulse will be generated by the AND gate, hence there are no correction pulses produced by PFD. In fact, there are still UP/DN pulses of width equal to the AND gate delay and reset delay, but the charge pump cannot respond to these tiny pulses because of the gate inertia of its switches. In this situation, the output of the PLL would be allowed to wander back and forth to levels where the PFD reacts. This undetectable phase difference range is known as the ‘dead zone’ in the PLL. This leads to unwanted jitter at the output of the PLL. In the presence of the dead zone, the total jitter of the phase detector is the sum of dead zone and correction pulse. A dead zone would cause the PFD input-output characteristics to change to that shown in Figure 6(c) .

By adding a delay element in the PFD to overcome the dead zone issue, when FREF = FBK, the PFD will generate UP and DN pulses but of very narrow width. These narrow pulses overcome the inertia of the PFD gates and the CP. This allows the PFD/CP combination to act on even the smallest phase error, thus avoiding a potential dead zone in the PLL. When the difference between these current pulses is averaged over a reference clock, a voltage whose value is a linear function of the phase difference between the two inputs is produced. This relationship between average voltage and phase difference is called PFD characteristic. Figure 6(a & b) shows the ideal and practical characteristic of the PFD.

Figure 6: PFD characteristic (a) ideal PFD (b) practical PFD with delay element (c) practical PFD without delay cell, showing dead zone

Charge pump
The purpose of the charge pump (CP) is to convert the PFD pulses to current pulses. These pulses are then conditioned by the filter before being fed to the VCO. A simplified schematic of a CP can be seen in Figure 7. It consists of a current source (IUP), a current sink (IDN), and two respective switches (P0 and N0). The UP signal from the PFD switches the IUP current source onto the filter and increases Vctrl voltage, while the DN signal from the PFD switches the IDN current sink onto the filter to decrease Vctrl voltage. When both the UP and DN signals are low, the filter sees the CP as a high impedance node. Ideally, if IUP equals IDN, then there will be no net change in Vctrl when both signals are either high or low simultaneously.

Figure 7: Block diagram of charge pump

Charge is proportional to PFD pulse width, i.e., Qcp = IUP*TUP – IDN*TDN

Low Pass Filters
A low pass filter (LPF) is used to convert the current pulses into average voltage. A typical schematic of a LPF is shown in Figure 8 .It integrates charge-pump current into CL to set the average controlvoltage. The resistor (RL) provides instantaneous phase correction andhelps improve the stability. Cs is to prevent the voltage jumps on theVctrl by smoothing ripples on Vctrl. For a simple RLCL filter, the loopequations are of second order. A second order system can be designed tobe unconditionally stable. In a charge-pump PLL, a switched currentsource is used to inject the charge into the loop filter. When thecurrent source turns on, a large drop can be created across the resistorRL, which would result in a momentary excursion of the VCO frequency.The extra capacitor CS helps to filter out the jumps in frequency,providing a smoother response. Depending on the application, the LPF canbe single-ended or differential.

Figure 8: Second order low pass filter

VCO Architecture
Avoltage-controlled oscillator (VCO) is one of the most critical blocksin a PLL. It generates the oscillation frequency of the PLL system thatis controlled by the Vctrl voltage from LPF stage. The VCO mostlydetermines the performance of the PLL in terms of power and jitter. AVCO generates an output frequency proportional to the input controlvoltage. Figure 9 shows the behavior of VCO frequency on a changing Vctrl.

Figure 9: Vctrl vs. VCO frequency

ForCMOS-based VCO designs in current technology, LC and ring-based VCOsare typical choices used in PLL designs. LC VCOs have superior phasenoise performance compared with ring VCOs. However, an LC VCO has asmall tuning range, large layout area, and higher power.

Theusual way of implementing a VCO is by forming a ring oscillator that canachieve its oscillations at low voltages. “N” numbers of identicalstages are used to form a ring oscillator. Each of the stages is called adelay cell. A CMOS delay cell is comprised of PMOS and NMOStransistors. It provides delay between input and output, and this delayis proportional to the control voltage. The mechanism for controllingthe delay of each inverter is to limit the current available todischarge the load capacitance on its output. The oscillation frequencydepends upon propagation delay per stage and number of stages. Eachdelay stage can be either single-ended or differential. A single-endeddelay cell has the advantage of lower device noise and thus lower phasenoise. But due to the single-ended nature, the power supply noiserejection of the VCO will be inferior compared to that of thedifferential VCO.

Figure 10: (a) Five-stage, single-ended input ring oscillator (b) Four stage differential input ring oscillator

Inring oscillators, the last stage is connected to the first stage ininverted mode; i.e., a phase shift of 180o. The remaining 180o phaseshift should come from the delay stages. The frequency of oscillation isthe frequency at which phase shift for all combined delay stages andfeedback is 2Π. To guarantee the oscillations, the closed loop gainshould be unity with a phase shift of 2Π. This means that for anoscillator with single-ended delay stages, an odd number of stages arenecessary for the dc inversion. If differential delay stages are used,the ring can have an even number of stages if the feedback lines areswapped. Examples of these two circuits are shown in Figure 10 .

Supposeeach stage provides a delay of Td. The signal goes through each of the Ndelay stages once to provide the first phase shift in a time of NTd.Then, the signal must go through each stage a second time to obtain theremaining phase shift, resulting in a total period of 2NTd. Therefore,the frequency of oscillation is FVCO = 1/2NTd. The delay of eachinverter can be controlled by limiting the current available todischarge the CL. Lowering Vctrl reduces the discharge current, hence itincreases Td.

Replacement of local oscillator with IC
Byintegrating the above defined blocks (PFD, CP, LPF, and VCO) in adefined order, we can implement a PLL system on a single silicon IC. Theoutput of the PLL can then be given to different on-chip dividers togenerate different frequencies. The output of each divider is thenpassed through individual buffers to strengthen the signal drive level.This complete system can be integrated on a single IC that consumes lessspace, less power, and decreases complexity of the system.

Part 2: Phase-locked loops in an IC-based clock distribution system: Part 2 – Phase noise

Part 3: Phase-locked loops in an IC-based clock distribution system – Part 3: Other sources of phase noise

Ashish Kumar presently works with Cypress Semiconductor India Pvt. Ltd. as a StaffProduct Engineer. He holds a Bachelor degree in Electronics &Communications Eng. He also completed a PG Diploma specialized inAdvanced VLSI Design. His interests are in making hobby electronicprojects, debugging circuit boards, and dealing with complex analog anddigital circuits. He can be contacted by email: .

Sanjay Agarwal works as Sr. Product Engineer in Timing Solution, CypressSemiconductor, Bangalore. He holds a Master of Technology degree fromIndian Institute of Technology Kanpur, specialized in ElectronicMaterials, device fabrication, and characterization. He has authorednumerous technical articles in semiconductor electronics publications.He can be reached at .

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