Plurality debuts new Hypercore development tools - Embedded.com

Plurality debuts new Hypercore development tools

Tokyo, Japan – At the Multicore Expo Japan 2008 here, Plurality Ltd. released the beta version of an extensive set of development tools for its HyperCore Architecture Line (HAL) of manycore processors.

According to Plurality CEO, Igor Pe'er, the tools will facilitate the evaluation and widespread adoption of Plurality's technology. Manycore architecture ” from tens to thousands of cores per processor ” is widely acknowledged as the natural evolution of multicore processing. HAL processors, he claims, will offer the highest performance at the lowest price per watt per square millimeter of any chip-level shared memory machine currently on the market.

“With multicore already mainstream, the future of computing inevitably will require massive parallelism performed on manycore processors,” said Pe'er. He said the architecture is positioned as a general-purpose accelerator for applications with a high degree of inherent parallelism, allowing HyperCore to act as an extension of the most popular processor architectures (x86, PowerPC, and ARM).

The HyperCore architecture includes 16-256 cores and multi-ported L1 shared memory in which each core is equidistant from the memory. A key component of the architecture is a hardware-based, low-latency, high-throughput synchronizer/scheduler that manages the cores according to a task map and balances the load among the cores.

The synchronizer/scheduler ensures scalable performance that enables nearly linear speedup, regardless of the number of cores in the processor. Among the many applications ideal for the HyperCore processor are image and video processing, video surveillance, gaming, network processing, security, and software-defined radio.

The HAL toolset includes a cycle-accurate simulator that runs on an x86 platform (Linux and Windows OS); a GCC cross-compiler (v. 4.0.1); GNU Binutils v. 2.18; a cross-debugger that works within the Eclipse development environment; and an emulator supporting Linux and Windows native environments.

Pe'er said the tools enable a gradual approach from exploring parallel decomposition with the emulator to precise evaluation of the performance of a 256-core system with the simulator.

The company's serial-like task-oriented programming model enables developers to easily write code for computations that are offloaded from the main processor. It simplifies the recompilation of serial code to parallel code and enables intuitive parallel programming of new applications.

He said the manycore development tools are currently being evaluated at the University of Otago in Dunedin, New Zealand. Several labs in the Electrical Engineering department at the Technion ” Israel Institute of Technology in Haifa, Israel also are checking the tools.

Pe'er said Plurality is developing acceleration boards that interface to a main CPU via a PCI Express connection and AMD's (NYSE: AMD) HyperTransport link. Plurality is a partner in AMD's Torrenza initiative, which enables hardware manufacturers other than AMD to connect a co-processor to an open CPU slot on the AMD Opteron 64 via its HyperTransport link.

The beta version of Plurality's development tools is available immediately at no charge and can be downloaded from the Plurality Web Site.

Pe'er said Plurality will release an FPGA-based 32-core evaluation board during Q2, 2009. A 64-core chip (HAL-64) will be introduced during the second half of 2009, along with an acceleration board that includes the HAL-64 processor.

To learn more, go to www.plurality.com .

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