STMicroelectronics announced the availability of memory solutions using package-on-package (PoP) technology, a packaging technique that saves board space when using high-density memory and a complex microprocessor. Such a combination is typically found in high-end mobile handsets.
The PoP structure allows two BGA (ball grid array) packages to be stacked on top of each other. The bottom package features the normal array of metallic balls, or bumps, on its underside, but also has an array of footprints (lands) on the top surface that can receive a mating top BGA package. Industry standards are being defined by the JEDEC association.
The technique enables devices to be assembled in a vertical stack consisting of a discrete logic device, such as a baseband or application processor, with a memory BGA package soldered on top. Standardized “ball-outs” route signals between them.
Manufacturers can source and test the typically complex memory system and logic device separately.
The first available samples are 12- by 12-mm (128 balls) and 14- by 14-mm (152 balls) package sizes, with a 0.65-mm ball pitch. Both split bus and shared bus architectures are supported. Further information can be found at www.st.com.