Multichip packages (MCPs) have long met the need to pack moreperformance and features into an increasingly small space. It seemsnatural to see the extension of the memory MCP to include ASICs such asbasebands or multimedia processors. But here, we run into thedifficulties of development and ownership/reduction costs.
How do we address these problems?
Today, a package-on-package (PoP)concept is becoming widely accepted. Combo memory (flash and RAM)products combining multiple flash NOR and NAND with a RAM in a singlepackage are widely used in cellphone applications. These single-packagesolutions are the MCP, system-in-package (SiP) and multichip module (MCM).
The MCP in cellphone applications began by combining what is nowconsidered to be relatively low-density combinations, such as an 8Mbitflash and 2Mbit SRAM.
As the memory requirements of the cellphone grew, the flash densityincreased with the NOR flash and the introduction of the NAND, and theSRAM was replaced by the pseudo SRAM (PSRAM).
Size, performance issues
The demand for more features in the ever-smaller form factor ofcellphones contributes to the need for MCPs. However, developingsolutions to enhance performance and keeping the small size poseadditional challenges.
The basic concept of the SoC is to integrate more components into the same piece of silicon toreduce size and cost while enhancing performance. In the cellphonemarket where project life spans are short and costs are aggressive,however, SoC solutions have a limitation.
From the memory-configuration point of view, where a large amountof logic is required with various types of memories, mastering thedifferent disciplines in design and technology can be a challenge thatmay affect the development time and flexibility required by theapplication.
From a silicon point of view, having the basic components separatedyet manufactured in a different technology would address the problem.The memory and the ASIC areassembled in the same package. However, there are two main areas ofconcern: SiP's cost of production with respect to yield and SiPinflexibility.
SiP's cost of production with respect to yield—In developing MCP ofany configuration, the final package and assembly yield is a product ofall the MCP elements' yields. For example, let's consider that eachcomponent has a yield of 90 percent and the MCP is made of four dice.Its overall yield is 90 percent x 90 percent x 90 percent x 90 percent.
A low yield cannot be considered mass-producible to serve a veryhigh-volume consumer market, where there is continuous pressure onprice. Known good- die programs are normal practice when consideringMCP configuration to keep yields at an acceptable level.
The memory and the baseband can contribute to about 25 percent of acellphone's BOM, depending on the features and specifications. The SiPthat combines memories with a baseband or co-processor will have arelatively high cost, and the complete SiP will be rejected if any ofthe components inside does not meet the spec.
The introduction of SiP is also limited by the availability of all thecomponents at the same time. And to achieve a competitive solution, allthe components must be produced in the most cost-effective technologyfrom the beginning.
This is further complicated by the fact that the developmentresources and time required are different between the ASIC and thememory. In many cases, these are produced by different companies.
This means that synchronizing on the availability is very difficult.Only a broad-range IC supplier can source most components internallyand meet timing demands.
Once the SiP is developed and available to the cellphonemanufacturer, changing any component inside the SiP for cost reduction(due to availability of new technology, for instance) could requirere-qualifications of the complete SiP. This is a long and costlyprocess.
The PoP concept separates the ASIC from the memory. The developmentand introduction of each component can take individual paths. Thesolution is achieved by assembling the two packages on top of eachother. The top package's solder balls bond directly onto landing padson the top surface of the bottom package (Figure 1, below ).
|Figure1. The bottom package typically contains ASIC baseband application or amultimedia processor. The top package typically contains a combinationof memory devices (flash and RAM).|
The bottom package typically contains ASIC baseband application or amultimedia processor. Memory modules for the bottom package are alsoavailable, allowing multiple stacks of memories, if required. The toppackage typically contains a combination of memory devices (flash andRAM).
The PoP solution provides greater PCB-space savings, compared with atwo-package solution. The proximity of the two components means thatperformance can be optimized. Working with a memory interface that runsat 100MHz and above, special guidelines and techniques are used for thesignals and power lines in the design of the packages to ensure signalintegrity.
The package characteristics play a key role in the overallperformance of the system. Design verification and simulationmethodology that were once part of the system design are now used todevelop the PoP.
The PoP solution allows the manufacturer to independently source thebottom and top package from different suppliers. As with many newdevelopments, there can be various proposals, as in this case for thephysical size and the ball-out of the respective pieces.
Within the Jedec standard, multiple options for the packages areincluded with variations in physical size and the electrical ball-out.The choice of standard to be used is based on the availability of boththe top and bottom package. The Jedec standard JC63 covers ball-outsand bus combinations, while the Jedec standard JC11 covers mechanicaldimensions.
The package size governs the area used on the PCB, and the packagethickness controls the profile, which is made up of A1+A2+A3 (Figure1). The overall package height needs to be maintained while allowingfor the top package standoff A2.
This dictates the space available for the bottom die and mould cap.The balls of the package are arranged in two rows around the perimeter.As seen in Figure 2, below ,dimensions D and E provide the body size, and e and b define the ballpitch and ball diameter.
|Figure2. Reducing the ball size and pitch would make additional signals onthe given parameters available|
Reducing the ball size and pitch would make additional signals onthe given parameters available and thus allow additional functionality.Finer ball size and pitch packages are in development and are includedin the JEDEC standards.
1. Pre- and post-reflow ball height that will dictate the standoffA2 in Figure 1 in the end;
2. Top and bottom warpagecharacteristics across the applications' temperature range and thereflow temperature profile.
In applications requiring a small form factor and high performance,the PoP provides a way for the components to follow an independentdevelopment path. Additionally, the two elements can be separated,giving flexibility greater than that achieved by an SiP or SoCsolution.
The PoP solution minimizes the space requirement and increasesmemory flexibility for the system designer. In the manufacturingprocess, it allows for separate sourcing and testing of the typicallycomplex memory system and logic device, simplifying assembly flow forhigh performance mobile multimedia products.
Vijay Malhi is Regional MarketingDirector of STMicroelectronics,Memory Product Group, Asia-Pacifi c
To read a PDF version of this story, go to “Packyour pocket gadget with PoP.”