POWER - Calypto uses sequential analysis to lower device RTL power - Embedded.com

POWER – Calypto uses sequential analysis to lower device RTL power

Santa Clara, Ca. – Calypto Design Systems Inc. has developed what it says is the industry's most accurate register-transfer level (RTL) power analysis capability by applying its patented sequential analysis technology.

Used to enable accurate power measurement in its PowerPro Analyzer tool, the technique performs sequential analysis of the entire design, delivering power measurement results that are significantly more accurate than the decade-old RTL power analysis tools in use today.

According to Tom Sandoval, chief executive officer of Calypto, previous tools have been based on combinational analysis which limits the accuracy of switching activity propagation compared to the actual sequential circuit activity.

“Sequential analysis ensures switching activity propagation estimated by the tool closely correlates with real life circuit activity,” he said.

By dramatically improving RTL power analysis accuracy, he said PowerPro Analyzer will enable designers to finally move away from time-consuming, gate-level power analysis flows.

“These flows require designers to run complex gate-level simulations in order to provide the power analysis tool with accurate design behavior that emulates real-world functionality,” said Sandoval.”Running those same simulations at the RTL level improves efficiency by 10x, often reducing the overall power analysis task time from days to hours.

“Moreover, RTL-level simulation is part of the standard simulation regression method used by designers to verify their design.”

The RTL simulation results can be provided to Calypto's PowerPro Analyzer without adding to design schedules.

“The inaccuracy of existing RTL power analysis tools has limited their adoption and forced the industry to continue using complex, schedule-extending, gate-level power analysis techniques,” said Sandoval.

Where older solutions use simplistic propagation engines that do not correlate with real circuit behavior, he said, Calypto's sequential analysis based propagation engines capture temporal and spatial correlations across registers that simply cannot be taken into account by obsolete, combinational analysis-based solutions.

Because clock trees consume a significant amount of power in a design, he said, understanding how to model a clock tree with a substantial amount of clock gating is critical to accurate RTL power analysis.

Calypto's RTL power analysis capabilities have been integrated into a new version of PowerPro Analyzer, which can be used as a standalone tool for RTL power analysis in SOC design flows.

PowerPro Analyzer with block-level power analysis will be available in October and chip-level power analysis will be available in February 2010. The tool will be offered for a list price of $50,000.

PowerPro CG and PowerPro MG, RTL optimization tools based on sequential analysis, each list for $295,000 and include PowerPro Analyzer. PowerPro CG is an automated clock gating power optimization tool that reduces power by up to 60 percent with little or no impact to timing or area.

PowerPro MG is an automated memory power optimization solution that takes advantage of the low-power control options available in today's on-chip memories to reduce both dynamic and leakage memory power with little or no impact to timing or area.

To learn more, go to www.calypto.com.

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