In the first part of this article series, we explored how to achieve a known (deterministic) phases for all channels within chips integrated with multiple digital signal processing (DSP) blocks, wideband digital-to-analog converters (DACs), and wideband analog-to-digital converters (ADCs). We started with a high-level system block diagram employing a subarray clock tree structure and described a multichip synchronization method. In this second part, we’ll explore PLL synthesizer phase adjustments, scalability to multiple subarrays, and system-level calibration algorithms.
PLL Synthesizer Phase Adjustments
The chosen PLL synthesizer ICs have been selected to allow for relative sample clock phase adjustments injected into each digitizer IC. Thermal drift, and the resulting PLL phase drift between the sample clock and the SYSREF of each IC, is compensated by creating a feedback mechanism that ensures that the first transmit channel of each digitizer IC is phase aligned to the first digitizer IC’s first transmit channel. To achieve this feedback loop, the first transmit channel of each IC outputs a signal that differentiates itself from the other transmit channels, as shown in Figure 1. These four signals are combined and sent into a common receiver, which for this system is labeled Rx0.
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Figure 1. A PLL synthesizer phase adjust feature allows the first transmit channel of each digitizer IC to be aligned across the subarray. (Source: Analog Devices)
Simultaneous receive data is obtained for all receive channels, which then allows users to apply cross-correlation techniques and determine the complex phase offsets between these four transmit channels, ΦTxOffset. The PLL synthesizer ICs contain within them a voltage controlled oscillator (VCO) that is operating at a frequency ƒVCO_PLL.
The measured phase offsets ΦTxOffset are then related to the required PLL phase adjustment ΦPLL_Adj and the RF frequency ƒcarrier such that:
Using this formula, the PLL synthesizer phases can be adjusted by a new known amount to establish a common transmit baseline between all digitizer ICs for all power cycles, as shown in Figure 2. The open circles for each channel shown in Figure 2 correspond to the first power cycle, whereas all the other solid dots correspond to subsequent power cycles. As can be seen from this figure, the calibrated transmit phase offsets for the first (and second) channelizers of all digitizer ICs are phase aligned. The second channelizer of each digitizer IC is aligned in this instance as well, because two channelizers are used for each DAC in the system.
Adding this PLL synthesizer phase adjustment step prior to the MCS routines discussed in the earlier section thereby creates a deterministic phase across all induced thermal gradients within the system by forcing the system to the same sample clock-SYSREF phase relationship, which is manifested as a transmit alignment baseline across all digitizer ICs.
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Figure 2. By adjusting the PLL phase, the user can align the first transmit channel of all digitizer ICs. (Source: Analog Devices)
Figure 3 shows that an induced thermal gradient can be detected via the temperature measurement unit (TMU) on each PLL synthesizer chip. As can be seen from the blue trace in the bottom left of Figure 3, widely varying temperatures across the platform have been intentionally induced by applying different fan airflows to the system. Using the PLL phase adjustment for each IC, however, demonstrates that regardless of the airflow applied to the board, the calibrated NCO phase offsets for each receive and transmit channel are deterministic when forcing the first transmit channelizer of each digitizer IC to be aligned to each other. This is revealed by observing the tight cluster of the same color of dots on the top two plots in Figure 3 despite the different thermal gradients applied to the board during different power cycles.
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Figure 3. The MCS feature used in conjunction with the PLL phase adjust feature demonstrates power-up phase determinism for all receive and transmit channels, regardless of the thermal gradient induced on the platform. (Source: Analog Devices)
Shown on the bottom right of Figure 3 is the polled digitizer IC registers, which show the measured SYSREF-LEMC phase relationship after applying the PLL synthesizer phase offset. Note from the orange traces on the bottom-left plot that the PLL synthesizer phase adjustments fully compensate any measured nonzero SYSREF phases resulting from a different induced thermal gradient.
Many frequencies have been measured, all of which demonstrate deterministic receive and transmit phase. The specific frequencies chosen for this article are shown in Figure 4, and were chosen such that MCS is demonstrated over many induced thermal gradients when using noninteger multiples of the reference clock or the LEMC.
Figure 4. The RF frequencies used in this article are chosen to demonstrate MCS functions over a wide range of clock sources, including noninteger multiples of the reference clock and LEMC. (Source: Analog Devices)
Scalability to Multiple Subarrays
The data shown in this article is primarily focused on MCS performance at the subarray level, but there is also a need to ensure that these synchronization features are realizable at the larger array level and across multiple subarrays. To achieve this higher level of synchronization, an array-level clock tree is required to ensure that the SYSREF requests to each subarray shown in Figure 1 in Part 1 synchronously arrive at each subarray’s clock buffer IC. Then, given this criterion, each subarray can issue the required SYSREFs and BBP clocks as described earlier such that these signals arrive at the subarray digitizer ICs and BBP within the same sample clock cycle across the larger array. This array-level clock tree requires that the clock distribution to each subarray possesses the delay adjustment blocks necessary to achieve synchronous SYSREF request distribution to each of the downstream subarray clock chip ICs. In this manner, multiple BBPs connected to multiple subarrays are ultimately synchronized.
System-Level Calibration Algorithm
While the MCS algorithms shown in previous sections do provide power-up deterministic phase for each receive and transmit channel, these phases are not necessarily phase-aligned across all channels within the RF domain due to any differences in RF front-end trace lengths across channels. Therefore, while the MCS algorithms do indeed simplify the array calibration process, there is still a need to undergo a system-level calibration routine to align the phases of each RF channel within the system.
It is therefore necessary to develop an efficient system-level calibration algorithm in addition to performing the MCS algorithms. The system-level calibration method for this article utilizes a specific baseband waveform and is completely self-contained without the need for any external equipment. The system described in this article is capable of injecting separate baseband waveforms into each channelizer on the platform. Utilizing this capability, a baseband waveform consisting of a one-period pulse for each transmit channelizer is injected in the subarray, as shown in the bottom-left of Figure 5. Each transmit channelizer therefore outputs only one pulse. However, the waveforms are staggered across all transmit channelizers such that only one one-period pulse is output at a time throughout the system. The output of all transmit channelizers is combined within the RF domain and then split and sent back into all receive channels, as shown in the top of Figure 5. Finally, a simultaneous receive data capture is performed for all receive channels and the data is saved to a 4096×16 matrix, where 4096 is the sample size collected for all 16 receive channels.
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Figure 5. A system-level calibration algorithm is used in conjunction with MCS to quickly achieve alignment of all receive and transmit channels in the system. (Source: Analog Devices)
This data is then analyzed vertically along the first column (corresponding to Rx0) to locate the Tx0 channelizer pulse, as is shown in the top subplot on the bottom-right of Figure 5. After the Tx0 pulse is identified all other pulse locations are known and the complex phase of each pulse’s rising edge is calculated and saved to a 1×16 vector that corresponds to the measured phase offsets present at all transmit channels throughout the system. With this knowledge, and using Tx0 as the baseline reference, the complex phases of all transmit channels are then modified based on the measured offsets.
Similarly, since the same combined signal is being sent into all receive channels, the data is then analyzed horizontally along the matrix (looking across all receive channels). The complex phases of all receive channels are then measured with respect to Rx0 and saved to a 1×16 vector corresponding to the measured receive phase offsets present in the system. The receive NCO complex phases are then adjusted throughout the subarray to phase align all channels with respect to Rx0, as is shown by the in-phase (I) and quadrature-phase (Q) ADC codes for all 16 receive channels in Figure 6. It may be noticed that, while the plot in Figure 6 phase aligns all channels, it does not necessarily amplitude align all channels. However, using the on-chip finite impulse response (FIR) filters now present on these digitizer ICs, one could alternatively achieve amplitude and phase alignment across channels without the need to allocate power hungry FPGA resources to achieve the same result.
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Figure 6. 16-channel receive I&Q phase alignment is achieved with the aid of MCS and a self-contained system-level calibration algorithm. (Source: Analog Devices)
This system-level calibration algorithm is presently achieved in MATLAB® and takes approximately three seconds to complete. However, if implemented in hardware description language (HDL), this calibration time may be further reduced while maintaining a completely self-contained algorithm. Additionally, by relying on the MCS algorithms, if the system frequency and amplitude is known at boot-up, users can load phase offset values from a lookup table instead of needing to undergo the measurements described in this system-level calibration method. In this case, the system-level calibration method can be used to populate the phase offsets saved to a lookup table during a factory calibration.
A successful MCS process has been demonstrated using four Analog Devices’ AD9081 MxFETM ICs as the backbone of the subarray. Thermal gradients across the platform are compensated with the aid of phase adjust blocks within four ADF4371 PLL synthesizers. An HMC7043 clock IC is used to distribute the SYSREFs and BBP clocks required for the JESD204C interface. MCS algorithms within the AD9081 allow for simplified system-level calibrations and provide power-up deterministic phase for multiple frequencies and thermal gradients present in the system. An efficient system-level calibration algorithm is also presented that is used to populate LUTs during factory calibration, and therefore dramatically reduces system boot time. This platform is shown in Figure 7 and is called the Quad-MxFE. The system is available for purchase from Analog Devices. This work is pertinent to any multichannel system present in any phased array radar, electronic warfare, instrumentation, or 5G platform.
Figure 7. The Quad-MxFE platform is available for purchase from Analog Devices. (Source: Analog Devices)
1 Del Jones. “JESD204C Primer: What’s New and in It for You—Part 1.” Analog Dialogue, Vol. 53, No. 2, June 2019.
2 Del Jones. “JESD204C Primer: What’s New and in It for You—Part 2.” Analog Dialogue, Vol. 53, No. 3, July 2019.
|Mike Jones is a principal electrical design engineer with Analog Devices working in the Aerospace and Defense Business Unit in Greensboro, North Carolina. He joined Analog Devices in 2016. From 2007 until 2016 he worked at General Electric in Wilmington, North Carolina, as a microwave photonics design engineer, where he focused on microwave and optical solutions for the nuclear industry. He received his B.S.E.E. and B.S.C.P.E. from North Carolina State University in 2004 and his M.S.E.E. from North Carolina State University in 2006. He can be reached at Michael.Jones@analog.com.|
|Michael Hennerich joined Analog Devices in 2004. As a systems and applications design engineer, he has worked on a variety of DSP/FPGA- and embedded processor-based applications and reference designs. Michael now works for the System Development Group (SDG) as an open-source system engineering manager in Munich, Germany. In this role, he is leading ADI’s device driver and kernel development team, developing device drivers for all sorts of mixed-signal IC products and HDL interface cores. He holds an M.Sc. degree in computer engineering and a Dipl.-Ing. (FH) degree in electronics and information technologies from Reutlingen University. He can be reached at Michael.Hennerich@analog.com.|
|Peter Delos is a technical lead in the Aerospace and Defense Group at Analog Devices in Greensboro, North Carolina. He received his B.S.E.E. from Virginia Tech in 1990 and M.S.E.E. from NJIT in 2004. Peter has over 25 years of industry experience. Most of his career has been spent designing advanced RF/analog systems at the architecture level, PWB level, and IC level. He is currently focused on miniaturizing high performance receiver, waveform generator, and synthesizer designs for phased array applications. He can be reached at Peter.Delos@analog.com.|
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