Growing energy costs and the “green” revolution are driving designers to reduce the power consumption of SoCs used in today’s electronics systems. The most common method for optimizing power in these complex circuits is through clock gating.
Clocks that toggle unnecessarily are key contributors to dynamic power consumption in flip flops, related downstream logic, and in the clock network. Clock gating reduces dynamic power consumption by eliminating unnecessary clock toggling without affecting the functionality of the original design.
The goal of the designer, then, is to maximize the average clock-gating efficiency (CGE) of a design. CGE is defined as the percentage of time that registers in a design are clock-gated for a given stimulus or switching activity.
Maximizing CGE can be easier said than done. Designers may be able to make an “educated guess” about where to insert clock gating; however, once the register transfer level (RTL) modifications are made and RTL power analysis is run, the results may come back positive—power went down – or they may be negative—power remained largely unchanged or even increased after the changes.
Unfortunately, though, RTL power analysis tool results may not be very accurate. Precise analysis requires synthesizing the design and performing the power analysis at the gate level—a long and tedious process. In the often brief time allotted for power optimization during a project, design teams may only be able to complete one or two iterations, severely limiting power optimization.
Requirements for Power Regression Flow
Such a hit-or-miss approach to power optimization is ineffective and unproductive. A much more systematic and efficient method is to build a predictable power flow.
To be effective, designers need actionable information to identify where changes should be made, as well as the metrics to track whether the optimizations have been successfully implemented in order to converge on the lowest power implementation possible. This requires a power optimization tool with the following capabilities.
First, the tool should identify specific logical design optimization opportunities to lower power and automatically present them to the designer. Such optimization opportunities are uncovered by analyzing the behavior of the design over multiple cycles (sequential analysis) in order to locate redundant register writes and clock toggle. Once located, these optimizations may either be incorporated into a design automatically, or be manually implemented in the RTL by the designer.
Second, the tool should be able to provide hints for restructuring RTL that enable it to automatically find further optimizations. There are several such scenarios. For example, the tool can point out specific signals for which an earlier cycle version can be used to generate clock gating enable logic.
The designer would then provide such a signal from a preceding pipeline stage, thus enabling the tool to discover the specific optimization opportunity. In another example, the tool would prompt the designer to clarify clocking relationships. In general, the tool should not attempt to build logic that crosses clock domains.
However, if the user can let the tool know that certain clocks are always synchronous to each other (essentially the same clock), the tool could then create enable logic that it might have otherwise rejected.
Third, the tool should provide information about RTL code that should be re-factored in order to expose signals that can be used to reduce the size of the logic associated with a clock gating opportunity.
Because the tool should be capable of making a power savings versus area tradeoff for any new clock enable that it suggests, there may be situations where re-factoring would allow the tool to provide a user with a clock gating enable opportunity that would otherwise have been dropped.
In all these cases, the designer would be expected to modify the RTL design based on the information provided by the tool, rerun the tool, and then either manually add the new clock gating logic that is provided, or allow the tool to automatically add the new clock gating logic to the RTL.
Finally, the power optimization tool should provide certain metrics that highlight areas in a design where the designer should consider micro-architectural changes to enable clock gating.
For example, based on switching activity propagation or analysis of the design for redundant writes, the tool should identify areas in the design where registers have high clock toggle rates with little switching in the associated datapath. It should also be able to identify registers that are frequently updated with new data, but where the registered data is rarely used downstream.
Power Optimization through Power Regressions
Running power regressions on a weekly basis (Figure 1, below ) using the tool described in the above sections would provide feedback to designers and project management about the progress of power optimization for a given design. This would enable milestones associated with meeting design power optimization goals to be tracked and linked to project timelines.
|Figure. 1 Power Optimization Regression Flow|
Weekly updates would allow designers to track progress/trends of the design, ensuring that the power optimization the design team was directed to perform during the previous week delivered the expected improvement. These trending metrics would provide project management with the data required to make decisions on design status.
As the RTL design matures week-by-week, the overall CGE and register power savings will saturate indicating a power goal exit criteria similar to bug rate criteria associated with functional verification for finalizing an RTL design. Late-stage tool runs should show no remaining power optimization scope, as illustrated in Figure 2 below .
|Figure 2. Power Optimization Curve|
Current methods employed by designers for optimizing power are inefficient and unproductive, making it difficult to know when a design is fully power optimized. The solution is to use a power optimization tool that can be run in a regression mode which creates a feedback loop to designers and project management.
This will ensure that the optimizations and hints provided by the tool are appropriately utilized according to the project goals and timelines. A power regression flow would allow designers to gauge the thoroughness of power optimization for a design, ensuring that the design is power optimized to the greatest extent possible.
Venkat Krishnaswamy is Vice President of Applications Engineering & Services and Founder of Calypto Design Systems in Santa Clara, CA. Prior to Calypto he held senior design, test and architecture positions at Sun where he worked on the UltraSparc T1 processor. Prior to joining Sun, he was a member of the Pentium4 design team at Intel where he held DFT, methodology and tool development positions. He holds a doctorate in Computer Science from the University of Illinois at Urbana-Champaign, a master’s degree in Electrical and Computer Engineering from the University of Cincinnati, and a bachelor’s degree in Electrical and Electronics Engineering from BITS, Pilani, India. His email address is email@example.com .