Primitive tools slow analog/digital integration - Embedded.com

Primitive tools slow analog/digital integration

Consumer demand for multimedia on small, low-power embedded and mobile devices is fast moving the industry into an era of billion-transistor systems-on-chip. But there is a speed bump on the road to a smooth migration: the not-so-easy integration of analog/mixed-signal circuitry with high-performance digital elements. Unlike digital circuits, in which the latest of electronic design automation tool methodologies can be used, analog/mixed-signal designs operate by much different rules. Going to smaller geometries not only fails to yield better analog performance, it sometimes lessens it.

Designs that do not require bleeding-edge performance can get quite good analog performance using the few EDA tools available. But high performance in submicron system-on-chip (SoC) designs requires much more attention to the details of the design, less automatic routing, placement and other automation, and more handcrafting of the transistors and associated resistive and capacitive elements.

“The modeling and simulation needs for analog/mixed-signal transistors in an SoC design are much more critical and harder to achieve, and will take a while to resolve,” said John Kusching, vice president of engineering at QualCore Logic Inc. (Sunnyvale, Calif.). “But at the very least, even if handcrafting analog functions is absolutely necessary, we must find some ways to make designers' time doing these chores more productive.”

Each move to tighter geometries has been a problem for analog designs, in which high performance does not depend on smaller geometries, Kusching said. In fact, good analog performance often requires bigger transistors, higher voltages and more control of a lot of parasitic and leakage currents than is necessary on the digital side. “So when you see digital designers pushing for 90, 60 and 45 nanometers as fast as possible, you will also see a lot of reluctance from companies developing embedded designs in consumer and mobile electronics, which require a lot more analog functionality,” Kusching said.

Because his company is in the business of developing analog intellectual property (IP) for customers that do not have the expertise, such problems are money in the bank. “But that does not make the development of a sophisticated design with a lot of mixed-signal and analog functionality any easier,” said Kusching. “Developing a high-performance, gigahertz-level mixed-signal device-such as a phase-locked loop at 90 nm, for example-results in leakage current problems as much as two to three times that of a few generations back. Leakages at that level make MOSFET capacitors-a staple of analog design-act like resistors in parallel.”

Another problem, Kusching said, is simulation times. As far as they go, Spice simulators are essential in analog/linear design. “But as transistor geometries have gotten smaller, circuits more dense, and second- and third-order effects more problematic, analog Spice simulations get longer.” At 90 nm, they can take twice as long for the higher-voltage analog transistors. And compared with digital designs, there is a lot of grunt work involved, since parasitics and second- and third-order effects often require a lot of hand layout.

Jerry Doorenbos, design-engineering manager in Texas Instruments Inc.'s high-performance linear group, said there is a good reason why many standalone analog and linear functions are still done at half-micron geometries: “That is where the performance is.” In SoCs, the designer must always be ready to accept compromise, he said. If none presents itself, the engineer must find a digital workaround that makes it possible to work with analog functions that are not precisely those needed. “If you absolutely need the analog functionality and you need the performance,” said Doorenbos, “either isolate that particular function and create an additional external circuit, or create two SoCs, one with all of the analog functions aggregated and another with the digital.” The latter tactic “allows you to get the most performance out of each [SoC] without making the compromises you would have to if the two were merged.”

However, with the right tools to help specify exactly what linear mixed-signal functions are necessary, the job of integrating high-performance analog and digital circuits on the same SoC should be easier. “Rather than having to design a circuit that must fit a broad range of capabilities, the developer can focus on those parameters of the most importance, optimize them and make compromises on the rest,” Doorenbos said. But the geometry differences will always mean that a mixed analog/digital SoC will be a compromise. “A half-micron analog process will always produce better performance than a 0.1-micron or a 90-nm process,” he said.

Doorenbos described an option that is increasingly being used: incorporating extra digital functions that might obviate the need for the linear functions. They can be used “to deal with the compromises that have to be made on such things as accuracy, offset and gain errors, background and in-system calibration, allowing us to reduce the amount of analog,” he said.

Although Spice simulators and analog modeling techniques from the large EDA vendors have improved steadily, they still leave something to be desired, especially as SoCs move down to 90 nm and below, said Ross Hirschi, director of the Design Environment, Technology Solutions Organization at Freescale Semiconductor Inc.

“It may get even worse as we move down to tighter geometries,” he said. “Every step forward taken with Spice simulation accuracy and speed is offset by the larger set of variables that have to be considered as fabrication technology edges closer to quantum limits. As we inch into the nanometer range, the number of variables that must be considered increases several fold at each step. And despite the improvements in the EDA tools, they are not keeping up with the increases in the number of parameters that must be considered in advanced designs.”

Not only is this costly in terms of device characterization, it hits hard during simulation, both in terms of time and in the amount of computing resources that must be thrown at the problem.

Hirschi described a workaround that Freescale is actively investigating: “Multi-die packaging allows us to aggressively design for the best digital performance on one die and to optimize for analog on the other,” he said. “But going this route also causes problems in getting the appropriate EDA support, because most of the tools are not designed to support multiple process technologies or multiple dice.” Moreover, multidie packaging demands being “more aggressive during the testing and sorting prior to packaging because of the higher costs of packaging,” Hirschi said. “There are also issues related to how tight the links between the two dice must be and how much sensitivity there might be to attenuation and noise issues, among others.”

Deepak Shankar, president and CEO of Mirabilis Design Inc. (Sunnyvale), thinks a lot more work needs to be done at the system level, where the high-level functional blocks are laid out. “We have been talking to a lot of companies about how high-level system design tools like ours can be used to help in designs with a lot of analog and digital intermixed,” Shankar said. “And beyond more productivity-enhancing tools at the gate and transistor level, [customers] have been telling us there is a need for a way for the digital designers to specify to the analog designers in a white-board sort of way the specific analog functionality needed.”

The more specific such directions are, “the more leeway it gives the designers of the analog/mixed signal blocks,” Shankar said. “Rather than having to develop a design that is required to work under a wide array of circumstances, the white-board approach allows the digital designers to be quite specific in their requirements. This in turn gives the designers of the analog/mixed-signal blocks a better idea of where they can compromise and where they can't.”

Language support
At the transistor level, more-capable analog modeling tools are coming into wider use. The emergence of standards such as the AMS (analog and mixed-signal) modeling-language extensions to standard Verilog and VHDL holds a lot of promise, said Daniel Lee, technical-marketing engineer at Mentor Graphics Corp. Verilog-A (or Verilog-AMS) allows a developer to draw a subcircuit with the definitions of how to compute the sources and impedances in that topology. From that input, a computable model is extracted. VHDL-AMS, on the other hand, bases its analog modeling format on writing simultaneous equations-easy when only a few transistors are being characterized, but almost impossible for an array of hundreds or thousands of transistors.

“In terms of simulation in particular, analog has always been a tougher nut to crack than digital transistor simulation,” said Lee. “But there is now the promise of significant productivity enhancements in the design of analog circuitry in SoC designs with the emergence of methodologies based on VHDL and Verilog AMS.”

While AMS will not necessarily speed up Spice simulations, it does enable more-selective use of Spice. “Rather than forcing the simulation of all of the analog transistors, what AMS brings is the ability to determine exactly which transistors need to be simulated and which don't,” Lee said.

AMS gives the designer the ability to model a transistor, or a group or array of transistors, and create a mathematical model that approximates the performance. “Because such models are plug-and-play-compatible with Spice and EDA tools, the SoC designer can run a simulation quickly that gives a good approximation of whether it will work or not,” Lee said. “Because you are simulating an equation and not 1,000 or so analog transistors, simulation times are reduced enormously.”

The trade-off is that AMS models are more abstract, and do not cover all of the second-, third- and fourth-order effects found in an actual circuit schematic. Still, “there are several places such a capability can be used,” Lee said. “One is in high-level transistor and gate-level modeling during the exploratory stages of a design. Another is to provide the designer with a high-level, bird's-eye functional check to determine if the design is heading in the right direction. AMS gets the designer in the general neighborhood, allows him to pick and choose, and then do a Spice simulation only where it is actually needed.”

From the point of view of some digital designers, as SoC designs move above 1 GHz, digital circuitry get problematic, less predictable, harder to simulate. The same issues also arise as gate and transistor dimensions get smaller. For example, at 90 and 65 nm, critical effects like IR drop and device reliability must be analyzed at the transistor level.

“But the belief that digital designers need to learn more about analog to solve such problems is not true in the context of new solutions that are emerging,” said Mike Demler, HSIM product marketing manager at Synopsys Inc. “Digital designers are incorporating new tools into their flows to account for analog effects. AMS languages allow designers to put an analog block into their gate-level simulators without needing to know about transistors. And co-simulation of SPICE with a Verilog or VHDL simulator accomplishes the same thing, without requiring behavioral modeling.”

Also helping smooth out the bumps on the way to high density analog/digital SoCs are the emergence of analog IP companies such as Qualcore, Cosmic Circuits and AnSem, said Mentor's Lee. “The largest of semiconductor companies have the internal resources to support the kinds of investments in research, tools and building blocks to deal with analog design in SoCs and with the analog behavior of digital designs above 1 GHz,” Lee said. “But for the many small to medium-size companies developing such designs, the only option is going to an outside source, such as an analog IP house.”

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