DRAM: the field for material and process innovation

Arabinda Das - November 16, 2009


Since its introduction, DRAM technology has been a commodity product driven by cost and razor-thin profits. DRAM's achievement over the years is extraordinary; its capacity in 1970 was 1 Kb and today it is 2 Gb. As an analogy, if any financial budget were to multiply as fast as the DRAM capacity, the investment of $1 would return 2 million dollars in 40 years! In addition, DRAM chips have to be smaller and more compact than their previous nodes so that more dies per wafer can be generated to compensate for the increasing manufacturing cost of introducing new technology. Increased memory density and stringent cost reductions has made DRAM development the field for material and process innovations, forcing manufacturers who could not innovate to quit the DRAM arena.

The material and process innovations over the years are remarkable. Some milestones in process development are discussed in the following paragraphs. In 1991, the IBM 4 Mb DRAM was the state of art technology. It was using p-channel transistors in n-well and high aspect-ratio trench capacitors with p-type polysilicon. The CMOS technology was made in a shallow p-epi-layer on a p- substrate and LOCOS isolation was employed. The damascene process with CMP planarization was already used. Polysilicon gate electrodes and source/drain were silicided with titanium. In 1991, the concept of stacked capacitors already existed and was used by Hitachi. However, the major developments by Micron and Samsung using stacked capacitors came later.

In Figure 1, two DRAMs (Micron's 64Mb and Samsung's 512 Mb) spanning almost ten years are shown. Both of them were forerunners in their times. Micron's 64-Mb DRAM was in the market in 1999. It was fabricated in a double metal, quadruple poly, 0.24 µm CMOS process. This DRAM used shallow trench isolation and tungsten polycide for transistor gates. The DRAM cell (0.5µm2) used stacked cylindrical capacitors with hemispherical silicon grains (HSG) in a capacitor under bitline (CUB) architecture. As for Samsung, their 512-MB 90-nm DRAM device was in full production in 2007. It is quite similar to their current product. The device was fabricated using a 3-metal, 6-poly CMOS process. Capacitors were over the bitline (COB) with a cylindrical storage node and TiN/poly cell plate. The storage node was around 1.85 µm in height and the capacitors used high-k dielectric aluminum-hafnium-oxide. They also introduced recessed channel to overcome short channel effects and improve retention. The cell size was 0.076 µm2.

SEM cross-section of two DRAMs of different technology nodes.

The innovations continue. DRAM's evolution is different from that of SRAM and NAND and, in some ways, is even more challenging. It is enough to increase the density of transistors for SRAM and NAND, but for DRAMs the capacitors also have to be taken into consideration. To understand the innovations implemented in the new technologies, TechInsights recently analyzed and compared two current technology nodes of the three leading DRAM manufacturers (Samsung, Hynix and Micron). The analyzed memories were 1 Gb in size.

By comparing two process generations (60 and 50 nm) from each of the top three DRAM makers, the trends in technology transition, both within the manufacturers and across the industry, were revealed. The major challenge for DRAM makers in each technology node was the requirement of cell capacitance and low leakage currents. Irrespective of the node, a minimum capacitance of 20 to 25 fF is required, this also determines the sensing signal margins. The DRAMs of 60- and 50-nm nodes analyzed at TechInsights showed that all major DRAMS have some common points. All three used liners for STI, which is the smallest structure to fill and has aspect ratios between 3 and 4.4.1 STI structure with liners implies the STI gap-fill needs annealing in the oxidizing atmosphere. Additionally self-aligned structures, strain and mobility engineering and non-planar transistors are used in the memory array. The gate stack in the periphery (MOS transistors) is no longer a simple poly-stack with silicidation but now consists of several layers. Even pre-metal dielectrics do not have a single fill and often are not doped oxides. The capacitor modules, which are probably one of the most difficult DRAM process modules, are all 3D capacitors with high-k dielectrics. Moreover, the thermal budget of capacitors is decreasing so as not to degrade the device performance. Therefore all DRAMs at 60- to 50-nm nodes use a metal insulator metal (MIM) capacitor with carefully chosen high k dielectric.

Despite the similarities, the comparison report revealed many differences between the top three DRAM manufacturers as each one is trying to reduce its cell footprint. Different design layouts are adopted. The wordline pitch is always 2F (smallest feature size) but the bitline pitch is varying from less than 3F to 4F. The depth and spacing between recessed channels are being adjusted and using a raised source and drain is directly affecting the substrate doping and STI depths. In the capacitor module, the choice of using a single layer dielectric against sandwiched layers is being evaluated. Single layers are cheaper and render higher throughput but have higher leakage probability compared with sandwich layers. For the last three technology nodes, Micron alone has used Cu-interconnects. Using Cu brings in other challenges, such as anti-fuses and diffusion barriers; however, Cu also has many obvious advantages, such as lower interconnect line resistance. The significant difference between the DRAM manufacturers is how they scale their peripheries. This is measured in the die efficiencies, which are defined as the ratio between the area occupied by nominal number of physical cells and the die area. If a DRAM has a die efficiency of 55 percent, it implies that the memory arrays consume 55 percent of the die area and the remaining 45 percent is occupied by the periphery that includes redundancy lines, sense amplifiers, wordline drivers, fuse banks, edge-seal structures, etc. Increasing die efficiency and decreasing die area is the best way to increase Mbytes/mm2, which is essential for cost reduction.

Die area, cell area and die efficiency of three leading DRAM manufacturers.

Micron has the smallest die and smallest cell area for both the 6x-nm and 5x-nm process technology. However, Micron's 5x node loses 11 percent die efficiency compared with its 6x technology node, which indicates that its peripheral structures are not scaling appropriately, while Samsung and Hynix both increase their respective die efficiencies.

Future difficulties

In the future, scaling will become increasingly difficult as some structures, such as the capacitor height, do not scale much between different technology nodes. Capacitor-dielectrics, planar transistors in the periphery and non-planar in the array, increasing leakage issues and increasing bitline interconnect line resistance will continue to remain big challenges for each new node and innovative processes with efficient layouts will be required to overcome these technical barriers. As a consequence, the growth of memory density in DRAMs is slowing down but the number of DRAM units being sold every year is steadily increasing. DRAM makers are already tailoring their products to provide a wide range of memories with different speeds, sizes and power consumptions for server, PC-notebook and mobile handset users.

In the long term, the critical limit to shrinking DRAM architecture will be determined by the access transistors' leakage current and the capacitor's charge storing capacity. The standalone DRAM may phase out as complexity increases and perhaps reinvent itself as embedded DRAM or logic-memory and continue to remain the field for material innovation. p

1. Semiconductor Insights report available at http://www.ubmtechinsights.com/ReportProfile.aspx?ReportKey=5356


Arabinda Das is senior process analyst at Semiconductor Insights Inc. After Das completed his master's program in physics from the Indian Institute of Technology in Delhi, India, he obtained his doctorate degree from Univ-Paris-6 in 1996.