Analogy delivers simulator, redefines strategy

- December 03, 1998

Analogy delivers simulator, redefines strategy

BEAVERTON, Ore. — Analogy Inc., is delivering a mixed analog-digital simulator, built on a single kernel, to the Department of Defense (DoD) this week. At the same time, the specialist in mixed-signal simulation is redefining its strategy around the prototype VHDL-AMS simulator and will make the simulator a centerpiece of Analogy's simulation product offerings.

Analogy had developed the simulator under contract to the Defense Advanced Research Projects Agency (Darpa).

The goal of the new simulation strategy, which Analogy is calling "TheHDL," is to encourage wide usage of mixed-signal simulation for top-down design methodologies. "We need to build more of an infrastructure for mixed-signal modeling," said vice president Doug Lundin.

The single kernel represents a departure for Analogy, which had developed and championed Saber, a high-performance analog simulator. Saber was coupled to digital simulators via the Calaveris algorithm — often on a "simulation backplane" — as a means of performing mixed-signal simulation.

With the single-kernel simulator, the analog and digital portions of a circuit are still synchronized by means of the Calaveris algorithm. But the semantics of the new simulator will be more responsive to the needs and contingencies of digital designers than Mast, the long standing model-building language for Saber.

More significantly, Analogy hopes to build an open environment that utilizes mixed-signal models constructed with VHDL-AMS, Verilog-AMS, Spice and Mast.

Under a contract administered by the Air Force, Analogy had spearheaded the development of IEEE1076.1 - analog and mixed-signal extensions to the VHDL hardware description language. The Open Verilog International (OVI) consortium, of which Analogy is a member, is similarly driving the ratification of Verilog-AMS. Participation in these multicompany standardization efforts undoubtedly moved Analogy away from partisanship toward its own Mast language, and more toward its current ecumenical posture. "We're pragmatic," Lundin said. "We realize that Mast isn't going to have that kind of market clout."

Mast did not have all the semantics necessary to support digital simulation, Lundin acknowledged. There was no easy way to describe data movement across buses, for example, without describing the state of voltage level changes - pin by pin. VHDL and Verilog, essentially digital design languages, made user semantics closer to what digital designers are familiar with.

Ideally, the new kernel should be able to accommodate other model types, such as SWIFT, OLE and the complex models of Logic Automation, Lundin said. Getting the simulator to be "language friendly" toward both VHDL-AMS and Verilog-AMS will be the near-term challenge.

The simulator being delivered to Darpa this week does not yet support all of the VHDL-AMS language constructs, Lundin explained. Nor does it offer advanced features like Monte Carlo simulation. But the current delivery is meant to say "the strategy is real" and the company is on schedule for meeting its obligations, according to Lundin. Final installments on the Darpa contract will be made during the first and second quarters of 1999