Under the Hood: The race is on for 50-nm DRAM

Young Choi - February 09, 2009

Severe oversupply has resulted in steep price drops in 2008, forcing the swift retirement of 8-inch DRAM capacity and pushing forward to the 12-inch capacity in order to lower the DRAM production costs by major manufacturers. In 2009 it is widely expected that most manufacturers will migrate from 60- and 70-nm devices to more advanced 50-nm devices.

Samsung and Hynix, two of the industry's DRAM leaders, have already begun migrating their production of major products to the 50-nm class process node. Latest analysis on both 1-Gbit DDR2 SDRAM parts from Samsung and Hynix revealed very interesting trends from the two Korean rivals.

The two 1-Gbit DDR2 SDRAM devices that Semiconductor Insights (SI) has analyzed (shown in Figure 1) are from the 50-nm class process node. The analysis confirmed that the process node of the Samsung device is 58 nm; SI confirmed this by measuring multiple wordline and bitline pitches using cross sections obtained via a scanning electron microscope (SEM). The same measurement techniques were used to determine the process node of the Hynix device as 54nm.

Samsung 1Gbit DDR2 SDRAM

Despite the larger wordline and bitline pitch, Samsung's DRAM cell achieved smaller cell size by using a 6F2-based cell design. On the other hand, Hynix's 8F2 cell design showed a 16.5 percent larger cell than Samsung's. It should be noted, that despite the larger cell size, Hynix's 1-Gbit DDR2 SDRAM achieved an impressive chip size of 45.1 mm2, only 2.7 percent larger than Samsung's 1-Gbit DDR2 SDRAM. The floorplans for both devices look very similar; one exception includes Samsung design having two rows of pads in the central region; whereas, the Hynix design has all the pads aligned in one row.

In terms of DRAM cell and access transistor structure, the two rivals show very different approaches. As for Samsung's 58-nm process technology, the cell design appears to have been changed from S-RCAT (spherical-shaped recessed channel access transistor) to RCAT. It appears that the tight pitch of 6F2 cell design poses a challenge to design an S-RCAT-based cell. The Hynix's 54-nm process technology maintains the same 8F2-based S-RCAT structure for the cell and the access transistor. To compensate for the change from S-RCAT to RCAT, Samsung appears to have made the RCAT recess deeper than that of Hynix's.

Another significant difference is the number of metal layers contained in Samsung's device. The Samsung 58-nm 1-Gbit DDR2 SDRAM device used only three levels of metallization, metal 1 is tungsten, whereas the remaining two metal layers are aluminum based. This is a significant change given that Samsung managed to achieve a very competitive chip size with only three metal layers. Previous generations of DDR2 products from Samsung used four layers of metalization. Given the importance of cost reduction in the DRAM industry, combined with the recent steep decline in DRAM prices, Samsung's 58-nm process technology with three metal layers is expected to achieve much needed production cost reduction, helping Samsung remain competitive in these tough market conditions.

RCAT structure

Hynix's interconnect technology appears to be a traditional four-metal process--tungsten-based metal 1 and three aluminum-based metal 2, 3 and 4 layers have been confirmed by SI analysis.

After reviewing both companies' previous three generations of products, SI has revealed some interesting trends. Samsung introduced their 6F2 cell-based 512-Mbit DDR2 SDRAM at the 80-nm process node. At the same process node, Hynix's 8F2-based cell was 33 percent larger than Samsung's 6F2 cell. However, Hynix's design managed to compensate for the disadvantage of having a larger cell by achieving an impressive chip size with only 13 percent of the overhead against Samsung's design. Over the next two generations (60-nm and 50-nm class), Hynix pursued an aggressive scaling of their process node, reducing the die-size gap with Samsung. Hynix pushed 66 nm when Samsung was using 68 nm, and adopted the 54-nm process node as opposed to Samsung's 58-nm process node. These efforts have helped Hynix reduce the chip size gap with Samsung's counterpart product to less than 3 percent at 54-nm process node, while maintaining an 8F2 cell design.

Hynix 1Gbit DDR2 SDRAM

It appears that the aggressive scaling effort, combined with some innovation in circuit and layout designs have helped Hynix maintain its competitiveness in the DRAM industry using 8F2-based cell technology.

We have also noted the difference in cell size overhead between Hynix's 8F2 cells and Samsung's 6F2-based cells. As companies push the process technology forward, achieving smaller pitches for wordline and bitline, the 25 percent advantage of 6F2-based cell in a given process node is reduced.

At the 2007 Symposium on VLSI Technology, Samsung published a paper titled "Fully Integrated 56-nm DRAM Technology for 1-Gb DRAM." According to this paper, the 56-nm process developed had 6F2 cell with S-RCAT structure and four metal layers (one tungsten and three aluminum-based metal layers). This is in contrast with the production part that SI analyzed, which showed 6F2 cell with RCAT structure and only three metal layers.

This year's ISSCC 2009. program suggests that Samsung will present another variant of their 50-nm class process technology. A 56-nm monolithic 4-Gbit DDR3 with three metal layers (two copper and one 1 aluminum) would be the first 4-Gbit monolithic DDR3 and the first Samsung DRAM with copper interconnect technology. The larger chip size of 4-Gbit density and higher performance requirement of DDR3 SDRAM would have required copper interconnect technology. Samsung appears to have managed to use only three metal layers in this challenging design.

Copper interconnect

Use of copper interconnect in DRAM is expected to accelerate into the 50-nm class process node with the addition of Samsung and Elpida (which announced its 50-nm DRAM with copper interconnect late 2008), as well as Micron, which has been using copper interconnect technology for several generations.

Another new technology being introduced to DRAM is 3D (three dimensional) DDR3, using TSV (through-silicon via) technology. Samsung is expected to present their latest innovations in 8-Gbit 3D DDR3 with TSV at ISSCC 2009.

This is a clear sign that DRAM manufacturers are constantly making improvements to their process technology, maintaining their competitive edge against their competitors. As the process node reaches the 50-nm and 40-nm class, there are some early signs of technical challenges. Uniform scaling in both the wordline and bitline direction from previous 80-nm and 60-nm process generations appears to be changing. Scaling in one direction is more challenging than in the other direction. Clear definition of 2F x 4F (8F2 cell) or 2F x 3F (6F2 cell) for DRAM cell dimension gets a little tricky in some cases. We also see that access-transistor design becomes more challenging due to the reduced size of the transistor and increased need for leakage control through better isolation.

The DRAM industry has many different choices to make: different cell designs; 6F2 vs. 8F2 and 6F2 vs. 4F2, the selection of interconnection material; aluminum vs. copper and the number of metal layers to used (three vs. four).

Some recent trends that reduce the number of interconnect layers show the emphasis on cost-reduction efforts in the DRAM industry. These different choices will pose challenges to some manufacturers with less favorable technologies. Competition between manufacturers with different technologies and approaches will become more evident--manufacturers will be required to develop competing technology or to come up with innovative alternative solutions to overcome the challenges. All aspects of these changes are important for the DRAM industry to remain a viable business.

Young Choi is senior manager at Semiconductor Insights, which specializes in analyzing semiconductors.