By Dev Paul, Semiconductor Insights - June 10, 2004
In the commodity DRAM market, suppliers are constantly striving to minimize product cost structure. Reducing the size of the memory array and peripheral circuitry is key to the overall competitiveness of a given supplier. Most of the DRAM memories on the market today have a memory cell size of 8F2 or greater, where F is the dimension of the minimum feature for a given manufacturing process.
Semiconductor Insights (SI) has determined that the Micron MT48LC32M8A2TG-7E SDRAM (0.13-micron) and the MT46V32M8-6TG DDR SDRAM (0.11-micron) both have a memory cell size of 6F2, which they have achieved 4 years ahead of the ITRS roadmap. The roadmap calls for vendors to deploy production DRAM with 6F2 cell size technology in 2008.
In implementing 6F2 technology in production devices, Micron can potentially get up to 20% more die per wafer than its competitors. This is a huge advantage in the DRAM industry where a few points of margin on shipments can mean the difference between huge profits and red ink. What do its competitors need to do to compete effectively?
How is it that Micron made this leap 4 years ahead of the ITRS roadmap and what is the impact in the market? Micron has been working on 6F2 technology for several years focusing on all areas required to realize this innovation. Specifically, it leveraged leading edge capacitor technology and multiple years of internal 6F2 design effort to bring these products to market. SI found that the Micron 6F2 cell uses stacked cylindrical capacitors with hemispherical silicon grains (HSG) polysilicon and tungsten silicided cell plate in a capacitor over bitline (COB) structure.
The analyzed 6F2 capacitor over bitline (COB) cell in the Micron MT48LC32M8A2TG-7E SDRAM (0.13-micron) was found to have the following features:
*0.1-micron 2 cell size
*Half-BL pitch: 0.13-micron
*Half-WL pitch: 0.13-micron
*Silicided cell plate
*3 metal levels with W metal 1 High aspect ratio W contact plugs
By implementing the 6F2 cell, Micron has substantially taken the size of its typical 256 MB SDRAM one step further as shown in the tables below:
As Table 1 shows, with its implementation of 6F2 technology in 0.13-micron, Micron has shrunk the die of a 256 MB SDRAM in the same process from 66 mm2 down to 45 mm2, equating to an approximate 32% shrink in die size. A certain amount of this improvement can be attributed to the implementation of 6F2 technology. The cell size drops from 0.15-micron2 to 0.10-micron2, which is a slightly larger gain than one might expect from implementation of 6F2 technology alone.
Micron's 6F2 product in 0.13-micron achieves the same die size as a 256 MB SDRAM in 0.11-micron, providing Micron with a significant competitive advantage moving forward. Furthermore, Micron has also implemented DDR SDRAM in 0.11-micron technology combined with 6F2 cell, adding no further die size to the basic 0.11-micron SDRAM.
The cell size was seen to drop from 0.11-micron2 to 0.079-micron2 in line with what one would expect in dropping from 8F2 to 6F2. As Micron optimizes its implementation of DDR circuitry in 0.11-micron, further reductions in die size might be viable.
How this positions Micron
As a result of the 6F2 design innovation Micron improves its competitive advantage vis--vis the competition. It allows Micron to produce more die per wafer in an existing process, or use a more mature process to achieve the same die size as its competitors. In the cost sensitive DRAM market, Micron now also possesses a trump card with respect to potentially dropping prices and still being profitable in the market. Furthermore, it may be able to use this innovation to target high volume, low cost, small form factor markets like mobile phones with stacked NOR-NAND-DRAM multi-chip packages, thereby further diversifying outside the PC market.
Micron has always been competitive vs. other DRAM rivals with respect to die size offering many 256 MB SDRAM and DDR SDRAM products in the mid-70-mm2 range. Samples previously analyzed by SI across the DRAM market (see Figure 1 and Table 2), place well ahead of its competitors, with Samsung still several mm2 behind with offerings > 55 mm2. That being said, Samsung is improving its offering in Mb/mm2 in a 512 MB DDR2 device K4T51083QB-GCD5, with a die size of 99.75mm2 in 0.11-micron process technology (Source: Semiconductor Insights 2004). Regardless, it is still approximately 10% behind equivalent Micron offerings.
Required Competitor Actions
Micron's competition needs to strongly invest in R&D and circuit innovation that will move them forward with respect to implementation of 6F2 cell technology well in advance of the ITRS roadmap date of 2008. Competitors cannot afford to let Micron have this large advantage for a four-year span and enjoy the higher number of die per wafer and profitability.
Being 10 to 20% behind the competition with respect to die size for equivalent products in similar processes in a tight market like DRAM is not sustainable for any length of time. If Micron plans to deploy this technology across several product lines, it will hurt the competition. In addition to commercializing 6F2 technology in their own product, competitors need to look into alternative means of equivalent product cost reduction (wafer cost, yield, packaging).
Paradigm shifts in innovation in a competitive market like DRAM can provide huge benefits for the first player to bring that innovation to market. Micron has achieved that with the implementation of the 6F2 cell in its MT48LC32M8A2TG-7E SDRAM (0.13-micron) and the MT46V32M8-6TG DDR SDRAM (0.11-micron) products. For the moment, 6F2 provides Micron with a substantial competitive advantage.
Competitors need to react to this quickly on all fronts -- from implementing 6F2 technology themselves, to using more traditional means of reducing wafer cost, improving yield and reducing packaging costs. In the last few years, there have been few major design innovations that significantly impact DRAM economics -- Micron's 6F2 is one!
Further analysis of Micron and competitor products can be found at the Semiconductor Insights' Web site.