Intel's 22-nm process gives MOSFET switch a facelift

Arabinda Das and Alexandre Dorofeev, Senior Technology Analysts, UBM TechInsights - September 06, 2012


Consumer demand for higher performance and lower power has long been the driving force for CMOS technology. The continuous scaling of devices has advanced development of new materials, increased packaging density and added new functionality to the devices that incorporate these design changes.

Scaling involves the shrinkage of all dimensions of a MOSFET, the remarkable switch that allows current to flow in a channel when activated by a gate, then stopping all current flow when the gate is inactivate.

The MOSFET switch has been the cornerstone of many developments in microelectronics. As scaling continues beyond the 30-nm node, however, it has become increasingly difficult to maintain gate control over the channel. This phenomenon, known as short channel effects (SCE), includes all the negative influences associated with device miniaturization, like threshold voltage dependence on channel length. Over the years, IC manufacturers have employed three main approaches to mitigate SCE: source drain engineering, channel engineering and gate stack engineering.

For advanced technology nodes, all three approaches are combined. The Intel 22-nm processor, currently in mass production, is an industry first. UBM TechInsights had the opportunity to analyze the structure and electrical characteristics of this device.

The Intel CORE i5-3550 processor is a quad-core device, codenamed “Ivy Bridge”, fabricated with Intel’s 22 nm process technology and featuring Tri-Gate transistors. Traditional 2-D planar MOS transistors have been replaced with gates that straddle narrow silicon fins rising vertically from the silicon substrate. A thin, high-k dielectric separates the silicon fin from the metal gate on each of the three sides of the fin—one on each side and one across the top—rather than just a top electrode, as is the case with the 2-D planar transistor. Control of the current from the source side of the fin to its drain side is accomplished by a gate on each of the three sides of the fin (hence, “Tri-Gate”) (see figure below).


Figure: SEM tilted view of Intel's 22-nm Tri-Gate device (click on image to enlarge).

Tri-Gate is colossal leap
Intel’s Tri-Gate process uses its fifth generation of strained silicon engineering with raised source-drain and embedded graded SiGe for PMOS channels (which induces compressive strain) and embedded Si:C for NMOS channel (which generates tensile strain). Similarly, Tri-Gate represents Intel’s third generation of high-k/metal gates, which are now implemented in a FinFET structure.

Although the only major change from the 32- to 22-nm node is the introduction of Tri-Gate FinFET, this is not an incremental change. Rather, it represents a colossal leap. This advance is not only a major deviation in the 50-year history of planar transistors, but also a step into the realm of fully depleted channels.

Tri-Gate has several advantages. For example, the effective gate width is proportional to the fin height and can be increased without increasing the device footprint. Additionally, because the gate wraps around the fin, there is better control of the channel. The resulting device achieves high drive current, and low sub-threshold leakage current, verified in one of our electrical parameters reports. Another benefit is that the walls of the Tri-Gate offer a different crystallographic plane than the top of the fin. By orienting the Tri-Gate parallel or perpendicular to the "wafer flat," the mobility of the carriers can be influenced. Here, the PMOS transistors benefit from the higher mobility along the fin sidewalls.

The Tri-Gate structure brings with it process integration challenges. Epitaxial SiGe and Si:C islands have to be grown in a recess in a narrow Si fin rather than in an Si substrate. The fin pitch determines the transistor area and also brings constraints to the tilt angle of source and drain implants. One constraint is due to double patterning, which requires that all the fin pitches be the same size; if a larger gate width is required, then multiple fins have to be employed.

That means gate width is dependent on integral units of fins.

In their six-transistor SRAM cell, Intel decided to make the widths of pull-down (PD) transistors greater than the widths of access transistors (AC). Therefore, two fins are employed for the PD transistor, while a single fin is used for the AC transistor. The figure below shows a topographical image of the 6T SRAM, where N1/ N2 are NMOS_ PD; N3/N4 are NMOS_AC; and, P1/ P2 are PMOS pull-up (PU) transistors. Each N1 and N2 have two fins and the remainder have one fin only.



Figure: Topographical SEM image of the 6T SRAM array at the fin level with metal gates removed. The SRAM unit cell has been annotated; the SRAM array contains thousands of identical unit cell repeated in horizontal and vertical directions.
Fin patterning
Fin patterning is not straightforward; the fin is patterned directly on the Si-substrate and the STI structure and fin are etched simultaneously. Usually, STI structures have a positive taper for easier gap fill, while fins with vertical walls are preferred by theory and model simulations. For this reason, a multi-step etch process is suggested for these features. However, Intel’s fin cross-section (see figure below) resembles a solid trapezoid rather than a thin rectangle. The 18-nm-wide bottom provides a reliable base for the fin while its narrow top (just 7 nm wide) is appropriately rounded.
 
This feature geometry helps to avoid electrical field concentration in the corners. A small step at the onset of the STI structure may be an indicator of a thermal oxidation that was likely used to repair the etch-induced damage and define fin geometry (fin thinning and top rounding). The figure below shows that the high-k gate dielectric and work function metal layers wrap around the fin. There are several barrier and work function metal layers, and a thick W gate fill layer. All these layers need to be filled in a high aspect ratio trench. 

Figure: TEM cross-section perpendicular to Si fin and along a metal gate. High magnification image of the fin reveals atomic planes of mono-crystalline silicon fin (lick on image to enlarge).

The aspect ratio can be estimated from the cross-section taken parallel to the fins (shown in the figure below).  The gate length is about 30 nm and the depth of the trench during processing is about 110 nm, which leads to an aspect ratio of 3.5. After the deposition of work function metal, the aspect ratio increases for the deposition of W, as the width decreases but the height remains the same. In future generations, when the gate trench becomes narrower, the problem of metal gate fill may arise leading to gate conductivity problems. The Structural Analysis Report of Intel’s 22 nm Ivy Bridge processor from UBM TechInsights discusses in greater detail the work function materials, their composition; process flow and a complete review of the ten levels of metal interconnects.


Figure: TEM cross-section of PMOS and NMOS transistors in a direction parallel to their fins, highlighting the high aspect ratio for the replacement metal gate.

Process variability
Another challenge facing FinFET device production is process variability as small nanometer differences in the fin structure could make large impacts on device performance. With 193-nm immersion lithography, double patterning and other processing steps, the variation in the fin widths for 22-nm node is about 10 percent as shown in the figure below. These fluctuations could become significant for future fabrication production.


Figure: TEM cross-section perpendicular to the fins and along metal gate (click on image to enlarge).

Although the general concept has been widely researched since the 1990s, only Intel has successfully deployed the first FinFET in volume production.  Looking ahead, there are still several options available to drive continued scaling for the future generations: rotating the substrate; forming the FinFETs on silicon-on-insulator or even adopting the surrounding gate architecture.

The greater challenge for advanced technology nodes is not the physical limit of scaling, but rather manufacturability with high yield, which is dependent on low process variability. Over five technology generations (90 nm to 22 nm), Intel has steadily introduced incremental improvements to their source drain, channel and gate-stack engineering processes, but the majority of other process steps have remained unchanged. This incremental improvement process strengthens the existing integration process.

For the 22-nm node, there have been several tradeoffs between performance and integration schemes and multiple process challenges have been overcome. This have yielded improved device performance and given a total face lift to the venerable MOSFET switch.