If we can count on anything, we can count on signaling rates going faster and faster for printed circuit boards (PCB). We know from our experience that when electrical signaling rates reach 1Gbps and beyond on conventional FR4 based printed circuit boards, high-speed design, analysis and layout cannot depend on the standard rules of thumb. The rules have to change. This paper will discuss the implications of high signaling rates and how this will effect your board design cycle. Specific attention will be placed on general design concerns, on analysis and simulation issues and layout challenges.
At one gigabit per second and beyond the concept of high speed digital signaling begins to take on enhanced meaning. In order to support these bit rates there are several areas that designer must be concerned about. At these rates, bit periods are compressed. Setup and hold times are minimal. Clocks are often embedded in the data stream with special coding techniques or are delivered in parallel with the data path. There is very little room for error in either the design of these circuits, in their analysis or in physical layout. Minor errors accumulate and cause major issues.
Take a journey into these realms. At 1 gigabit/sec each bit is delivered in 1ns, a complete bit cycle time is 2 ns and the operating frequency is 500 MHz. To support this rate, signals rise and fall in less than 200 ps with significant harmonic content to 2.5-5 GHz. At 2.5 gigabit/sec each bit is delivered in 400 ps, a complete bit cycle time is 800 ps and the operating frequency is 1.25 GHz. To support this rate, signals rise and fall in less than 100 ps, with significant harmonic content to 5-10 GHz.
These are microwave frequencies that require extreme care. Printed circuit board traces no longer act like perfect conductors and lossless transmission lines. Vias no longer look like simple connections from one side of a board to another. Packages become significant elements in the design. Capacitors and resistors begin to look more similar than dissimilar. Even the interface between the package and the board becomes a significant engineering issue. Pads, anti-pads, and breakouts cannot be ignored. For the electrical designer all the “normal” rules of thumb begin to fall apart. To those familiar with the design, modeling and simulation of lower speed digital circuits a whole new set of understandings and intuitions must be developed. Layout and engineering must become integrated into the design process to ensure successful products that operate reliably.
Trace Impedance Selection, Trace Widths, and Dielectrics
The effects of trace characteristic impedance (Z0) and trace width selection become very significant at high-speeds. In general, gigabit-signaling systems use 100 W differential impedance traces. Why? Because this is the impedance of most external circuits to which boards interface. If 100 W differential impedance is required, then what are the options that a board designer has? Fundamentally, there are two. First, signals may be routed on outer layers as microstrip or on inner layers as stripline. Second, the trace width and dielectric thickness can be varied.
When looking at the trade-offs between microstrip and stripline trace construction there are several considerations. Manufacturing process variations for microstrip (outer layer) traces is much higher than for stripline (inner layer) construction. These larger variations are generally due to uneven plating of the outer layer copper and can result in significant trace width variations from board to board and across any one printed circuit board trace. These width variations make a trace look like it “wiggles” under microscopic examination and cause variations in its electrical properties, primarily characteristic impedance. In general, impedance control is much better for stripline than it is for microstrip. This causes perturbation of electrical signals carried by the trace, small reflections, loss of signal amplitude, and jitter. In a design with equivalent trace widths and impedance, stripline traces will show less impedance variation than microstrip. If impedance control is the primary design concern, then stripline is to be preferred over microstrip.
To achieve 100 W differential trace impedance, a variety of board stackups can be used. Wider traces require larger dielectric spacing. Narrower traces require smaller dielectric spacing. So what are the trade-offs here? Differential pair trace density is certainly one consideration, the narrower the traces the higher the densityno surprise. To compensate for the narrow trace, smaller dielectric spacing is used. These narrow dielectric spacings allow for more layers and less coupling (crosstalk) to adjacent differential pairs. All in all this is a pretty good trade-off. So why would a larger trace spacing be more desirable? Two answers: manufacturing variation and high frequency loss.
The manufacturing variation for etching a trace is generally a fixed quantity, based upon the process control of the board fabrication vendor. It is not uncommon to see trace width variations from ±0.5 mil to ±1 mil. These variations cause an overall variation in trace width. The%age of overall variation changes with the width of the trace. Wider traces have lower%age variation than narrower traces. This translates into better impedance control for wide traces when compared to narrow ones. If impedance control is the most important variable in the system, then wide traces will always be selected over narrow ones.
At high frequencies skin effect losses of the copper conductor and dielectric losses begin to dominate the overall amplitude attenuation of signals. Dielectric loss can be controlled through the use of low loss dielectric materials, if necessary, at significant (3-10X) cost impact. However, skin effect loss can only be reduced through the use of wider conductors. Essentially, doubling the width of a trace halves the overall attenuation of a signal due to skin effect. For high data rate differential pair signals being transmitted over long distances, reduction in attenuation is an important design consideration. Increased trace width can be used to partially offset conductor high frequency losses.
Packages, Stubs, and Vias… Oh My!
There are issues with high-speed signals before they are even off a device. High-speed signals are very sensitive to electrical stubs. With gigabit and beyond signaling, package stubs induce a significant amount of jitter. For this reason, many devices now parallel terminate on-die. When parallel on-die termination is not provided these package stubs can have significant electrical impact.
Many current rule-of-thumb terminations assume that the device package inductance is small enough to be electrically short relative to the rise time of the signal, and so we can treat device buffers as purely capacitive loads. But, as edge rates increase, the purely capacitive load assumption of an input is voided due to package inductance. Huh… so who cares?
At gigabit frequencies, inductance and capacitance combine to form resonance structures. When excited by sufficiently fast high bandwidth signals they ring! If the ringing is near to the frequency of the data transmission, then changes occur. The signal is jittered and moved in time and voltage. At 100 MHz a package that rings at a frequency of 1 to 2 GHz is not a large issue. Ringing dampens out in time to have negligible impact on the actual waveform. At gigabit data rates, uncontrolled, unterminated packages can create large signal jitter. Package stub quarter-wave resonance effects can be even more important than stub capacitance.
Even a via is a structure that will have delay and may or may not act as a stub, depending upon the structure of the pad stack and the entry and exit layer of traces from the via. Via delay in a 0.063 board is approximately 10 ps. For high performance signaling, even this tiny amount of delay can be significant enough to act as a stub. But for a backplane, which is often up to 200 mils thick or larger, vias can introduce huge stubs with delays approaching 30-40 ps. Anti-pad size will have a significant effect on the overall via capacitance and impedance, as will the size and number of via pads. Removal of unused pads will also vary these characteristics, as will counter-boring the via barrels. For gigabit signaling, even vias must be carefully engineered.
Differential signals also become much trickier at gigabit speeds. The primary reason here is skew. Differential skew, besides causing common mode currents, will cause a translation in time and voltage of the differential crossing point. This is serious. It causes the received Eye to close down and may be perceived as timing jitter. If the skew is greater than 100% of the edge transition time, then the eye becomes totally closed. (A 100% edge transition time skew causes the differential crossing to never be seen at the receiver.) This is true no matter what the bit period is and is dependent only on the edge transition time of the differential signals.
Some LVDS drivers have edge rates in the 100 ps range. For these, 100 ps of skew would totally close the eye, and 25 ps of skew would reduce the eye opening by 25%, a significant reduction in noise margin. In contrast, with 1ns edge rate drivers, like some of the “nice” LVDS devices, 25 ps of skew is not a big deal. This translates to only a 2.5% noise margin reduction. The moral of this story is: You need to know what your edge rates are in order to perform effective gigabit differential pair design and skew control.
Eventually differential skew causes the falling edge to overlap with ringing (noise) in the rising edge waveform. This causes the receiver output to switch at each crossing, first with runt pulses and then with increasing larger, overlapping pulses. As you can see, it does not take much voltage differential to cause the receiver output to switch. These are ideal simulations. In a real system, random and deterministic noise will increase the chances of data bit errors due to differential pair skew.
Differential Signal Layout
Differential signals must be routed carefully. The assumption that a PCB dielectric is homogeneous for both signals of a pair routed the same length in different geographic areas is false, for FR4 in particular. The dielectric constant of FR4 as seen by a trace is highly dependent upon the orientation of the trace over fiberglass bundles and the direction of the “grain.” Since fiberglass is porous, the water content of different areas of the board varies. This variation can cause large differences in its dielectric constant and the accompanying velocity of propagation. It is more likely that the dielectric can be considered homogeneous for tightly coupled side-by-side differential pairs than it can for weakly coupled differential pairs. It is generally most homogeneous for broadside-differential pairs, however, manufacturing tolerance issues preclude their use… except for those who have the time and money to control the manufacturing process.
Otherwise, weak coupling will subject the pair to susceptibility from other coupling sources. This coupling will cause differential skew. The net effect is that differential skew due to either mismatched trace velocities or additional coupling sources will cause voltage jitter in the received signal at the differential crossing. This jitter has the effect of reducing the CMRR of the system, closing down the received data eye, decreasing the noise margin, and increasing the overall bit error rate.
Overall, there are four specific criteria for routing differential pair traces at gigabit signaling speeds:
- Keep the traces tight and close together as compared to surrounding traces. The coupling from tight inter-pair spacing decreases the influence of other signals. This coupling also mitigates the effects of uneven board materials and properties.
- Keep the traces away from other traces. Coupling to other signals, including other differential pairs, will introduce noise and jitter that will increase the probability of bit errors.
- Look for coupling in the z-axis direction with other traces when using multiple asymmetric stripline layers between a power, ground, or power-ground pair. Coupling occurs not only on the same layer as a trace, but also on all layers that are adjacent to the trace. Z-axis coupling is often stronger than any parallel track coupling on a single layer and is one of the greatest causes of random failures and high bit error rates in differential systems.
- Keep differential pair routing as symmetric as possible. Differential pairs can be separated to navigate through pin fields, where absolutely necessary, but symmetry must be maintained. Symmetry in differential pair routing guarantees that any noise injected by external circuits, such as connector pins, will null and be rejected by the differential receiver.
Simulation Considerations Many simulator algorithms were designed to analyze slower-speed signals and they introduce errors when used for higher-speed ones. Below are some examples of simulation considerations to be aware of:
- Certain simulator algorithms have errors that accumulate when multiple trace segments are simulated.
- Approximations used in the extraction of trace and feature characteristics from PC boards can contribute to cumulative errors, especially in coupled transmission lines. When the resolution of the extraction is too high, the minimum segment length used in a trace extraction can be too small to be appropriately extracted. In this case the algorithm can either:
- Lump the small section into another section.
- Ignore the small section.
- Increase the small section to the step size.
Options b. and c. introduce errors. However, option a. can also introduce errors when coupling is considered. Modeling of a printed circuit board is always an approximation. The approximation accuracy is related to the size increment of the lumped elements which will be simulated and the method which was use to extract them. If our LC lump is too large (or has too low a bandwidth) then we introduce errors in simulations of cascaded systems. If our extraction LC lump is too large, then it becomes an algorithmic decision about how to handle board features smaller than the lump. With board feature sizes decreasing, and operating frequency increasing, it is very easy to extract garbage without knowing you have done so.
- Most models of common components are inexact at gigabit frequencies. Resistors have capacitance. Capacitors have resistance. Both have inductance. Device packages are commonly modeled in a simplified fashion. What is acceptable for 100 MHz bus simulations is often worthless for the simulation of gigabit signals.
- The decreased bit cycle time of gigabit signals increases the possibility of electrical influences, such as jitter, occurring and spilling over from one cycle to the many others. This effect, known as Intersymbol Interference (ISI), is simulated using long data bit streams with patterns, which represent normal random operation. Many simulators do not allow the incorporation of ISI patterns into the simulation environment.
- Presentation and extraction of simulation waveform information is just as important as the simulation itself. Many simulators do not allow for the display of “eye” patterns which are the standard method of visually displaying gigabit differential signals. The eye pattern view of a waveform encapsulates all pertinent information regarding that signal in one very compact display. When combined with ISI pattern simulation it is a powerful view of a differential system in action.
The speeding-up of electrical signals makes it much more challenging to implement designs; you certainly cannot count on using traditional design rules-of-thumb. The additional factor of deadlines can lead to quite a balancing act. It is key to know the edge rates of your signals, and to understand there are many ways these significantly impact both your design and your simulations. It is equally important to know that the modeling of these effects is not a trivial task. Old rules of thumb must be discarded. Old ways of layout must be changed. Old simulators and analysis techniques must be modified or replaced. These changes are all necessary in quality-engineered designs running at a gigabit per second and beyond.
About the Author
Rob received his BSEE and MSEE from Oregon State University. He hascompleted all but his dissertation toward his Ph.D. in electricalengineering. His research interest is the propagation characteristics ofsignal vias penetrating power planes. Rob also holds several patents.