Processor simulation models for CEVA cores facilitate system design - Embedded.com

Processor simulation models for CEVA cores facilitate system design

San Jose, Calif.&#151 CEVA, Inc. and CoWare Inc. have jointly launched Processor Support Packages (PSPs) that support the use of CEVA-TeakLite and CEVA-TeakLite-II DSP cores within the CoWare system-level design environment. The jointly developed models, based on the SystemC high-level design language, allow designers to quickly perform early architectural exploration and trade-off analysis before committing a CEVA-based design to silicon.

Using the CEVA PSPs and the CoWare Platform Architect environment for ESL design, designers can explore and verify alternatives for using different cores, busses and cache sizes, as well as simulate hardware and software operating together, all without having to commit to a hardware prototype. This early-stage exploration capability streamlines the overall design process and reduces time to market for complex system development.

The PSPs can be configured within the CoWare environment to create and analyze a variety of platforms based on the CEVA cores. Using the instruction-accurate model, CoWare's tool provides fast simulation of the system, including software running on the processors, to give designers faster and more comprehensive insight into design behavior and potential trade-offs to achieve design goals.

PSPs that support the use of CEVA-TeakLite and CEVA-TeakLite-II DSP cores within the CoWare ESL design environment are available immediately from CoWare. For more information about CoWare SystemC Model Library, CoWare Platform Architect, and CoWare's other products, visit www.coware.com. or visit CoWare at the Design Automation Conference, Booth 3173, July 24-27, 2006 at Moscone Center.

CEVA,Inc. (408) 514-2976www.ceva-dsp.com

CoWave, Inc. (408) 392-8513www/CoWare.com

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