PRODUCT HOW-TO: Using standards-based tools to scale chip designs to next-gen geometries - Embedded.com

PRODUCT HOW-TO: Using standards-based tools to scale chip designs to next-gen geometries

Layout for large digital IC designs is generally created using highly automated place-and-route (APR) tools. Although there are trade-offs for using APR instead of custom layout, the speed and confidence offered by APR far out weigh the compromises in area or performance for most designs.

But designs that require the utmost in performance and/or the smallest possible area are still done “by hand” using custom IC layout methodologies. In the next generation of custom chips, complicated rules, tight time-to-market schedules, and the sheer size and complexity of designs are making full-custom digital blocks increasingly difficult to implement.

Fully-automated APR flows cannot offer the kind of interactive control of the layout and routing that is necessary. Designers need a highly-automated yet controllable full custom digital IC design flow that optimizes performance, speed and area.

This article details how one digital IC design team at a large fabless semiconductor company in the consumer product market is leveraging standards-based tool interoperability to maintain the benefits of hand layout for large, performance-sensitive 40nm designs.

The team has deployed the integration capabilities made possible by the Silicon Integration Initiative’s (Si2) Open Access (OA) interoperability standardization effort with tools from multiple vendors to form a more productive custom IC layout flow.

Controllable automation
In designing high-volume storage solutions, the design team has for many years deployed custom IC layout automation for its analog and custom digital designs.

While analog designers have always used custom design methodologies, it is typically only when performance, power, speed or area requirements exceed the capabilities of APR tools that digital design teams turn to custom design tools and flows.

For optimal performance and cycle time, engineers use tools that employ advanced controllable automation techniques to create custom digital designs much faster and with less effort.

These include an advanced schematic driven layout (SDL) flow that uses highly configurable, process-independent parameterized cell technology and a device-level floor planning tool that offer the speed and control necessary to achieve the best possible performance and density without having to change design style or compromise the quality of the result.

Figure 1: Flight lines show connectivity and guide rule-driven manual routing.

Using the flight lines generated from the connectivity automatically carried over from the schematic (Figure 1, above ), the engineers then use the built-in rule-driven interactive router to wire critical nets by hand to meet demanding clock rate requirements that exceed 2GHz.

At this performance level, the routing of an individual net is especially sensitive to its environment and interactions with other routes, nets and even other layers.

To balance all of these elements, it is necessary for the design team to interact with all elements of their design environment. When handrouting, the design team is able to route, extract and evaluate the critical nets for timing and then modify them until the desired values are obtained.

Dealing with layout challenges
Although the custom layout and hand-routing approach was able to meet performance requirements, it was becoming increasingly more difficult to complete the next generation of custom digital blocks in a reasonable period of time.

As the designs got larger and more complex, layout designers encountered serious routing problems and found themselves designing-in white space (open areas) for routing channels, giving up density to make manual and point-to-point automated routing manageable in increasingly large blocks.

While the design team could still achieve performance targets, it often came at the expense of increased area, which was less than ideal given the cost-sensitivity of their market segment. In addition, the amount of time required to complete the design precluded trying more than a single layout.

A further challenge was introduced with the design team’s move to 40nm manufacturing processes to accommodate the increased performance requirements. At this node, blocks became too big (too many nets) and design rules too advanced for hand-routing and existing automated custom routing solutions.

There were no large scale custom routers that could provide the deep sub-micron DRC-clean and DFM-aware routing required for advanced processes.

The team initially attempted to use a hybrid flow, hand routing critical nets using the layout editor as before, and then using the digital router in their APR flow that supports advanced DRC rules to complete the non-critical nets.

Unfortunately, moving in and out of multiple tool sets was counter- productive. No matter how efficient the individual operations were, the custom and digital design domains did not work well together. In addition, this method was not interactive and caused the team to lose both hierarchy and connectivity information. More often than not, the automated router also re-routed some of the painstakingly-drawn critical nets, requiring extensive hand edits or yet another cycle through the router, or possibly both.

As a result, the design team spent six weeks moving the design back and forth, in order to converge on an acceptable, albeit sub-optimal, result. Automated routing, even for non-critical nets, might have improved the team’s productivity had it not impeded their ability to work iteratively. Also, there was no way to represent partial pre-routes and the sophisticated spacing constraints needed to guide the APR tools.

This, in turn, lead to bad parasitic interactions within the custom blocks that required laborious manual re-routes and multiple lengthy re-runs.

While automation typically improves productivity, in this case, it made a difficult process longer because designers could not control the results. Indeed, hand-edits of critical nets in a fully routed layout can take longer than routing by hand initially.

The team concluded that in order to achieve optimum results in less time it would require a heterogeneous environment that maintains hierarchy, connectivity and design integrity through controllable automation. Interoperability saves the day.

Figure 2: Si2 has made available an interoperable database for EDA tools called OpenAccess (OA).

The standards organization Si2 has made available an interoperable database for EDA tools called OpenAccess (OA) that has in recent years become the standard for custom design (Figure 2, above ).

Taking advantage of OA-RTM
A little-known feature of OA is the OA Run Time Model (OA-RTM) that can be used when running natively on OA as the in-memory model for EDA tools. This means that entirely different tools may operate on the same in-memory representation of the design data at the same time. Tools from multiple vendors that use the OA-RTM can work as seamlessly together as tools from a single vendor.

Using OA-RTM, a new high performance custom router from Pyxis Technology (Figure 3, below ) is able to work within the design team’s existing Laker custom layout environment running on OA.

Figure 3: Router recognizes and routes around blockages.

This very high capacity custom digital router is customer-qualified to create DRC-correct, DFM-aware routes at 45nm and below. It routes all levels of hierarchy and is incremental, meaning that it does not change existing critical nets created by hand.

When running the custom IC layout system, designers can select an area of the chip and have the integrated router route all of the nets within that window (Figure 4, below ).

Figure 4: With the ability to iteratively route, extract, analyze timing, modify and verify, the design team can reduce the design margins required to achieve their higher performance targets, while also reducing power consumption and area.

Gateways that force a particular routing channel, as well as blockages, changes, and fixed and existing routes are all recognized by the router without data translation or having to save the data to disk.

With this interoperable solution in place, the design team is able to create layouts as before using the automated custom IC layout system with SDL methodology.

Transistor-level routing is performed by the layout tool, as are the critical nets. Alternatively, pre-wires that define the routes for critical nets can be defined by the layout editor. Routing is performed in phases, starting with critical nets and then proceeding in prioritized groups (hierarchically), or entire blocks can be done at once in just a few minutes.

The design team is also able to take advantage of the custom router’s built-in extraction and timing engines for rapid feedback of parasitic interactions and simple timing. In this way, engineers can determine when the routing topology is “good enough” before committing too much to layout. Plus, the speed and controllability of this custom flow makes it feasible for them to quickly evaluate the placement of layout elements for optimal results.

The router can also add ‘dummy fill’ (extra pieces of metal commonly inserted into layout to increase the data density for process uniformity and planarization) to help locate potentially destructive parasitic effects, thus ensuring that foundry-implemented dummy fill will not cause unexpected problems.

By combining these capabilities with a highly automated custom layout system, the design team, in collaboration with its EDA vendors, have created a solution that enables fast, iterative ”what-if” analysis to simultaneously optimize the layout and routing.

With the ability to iteratively route, extract, analyze timing, modify and verify, the design team can reduce the design margins required to achieve their higher performance targets, while also reducing power consumption and area—all within less time than it previously took to implement a single layout.

Benchmarking the design
The chosen benchmark involved a critical, high-performance block that had previously taken six weeks to converge on an acceptable solution.

The performance requirements of this block conflicted with the area and power requirements which made it very difficult to complete successfully. To confirm the performance of the router, the existing routing was removed. The design was opened in the layout editor and the entire block was routed automatically within minutes.

To mimic the standard flow, additional versions were quickly generated in which some of the critical nets were routed by hand using the layout editor and the remaining nets implemented using the automatic router. No critical nets were altered during the automated routing sequence and no DRC violations were noted.

After this initial proof of concept, the design team has demonstrated with consistent results that large, high-performance custom digital blocks, which typically took three to six weeks to complete, can be created in less than one week with their flow.

This means the team can spend more time optimizing the performance, area and power consumption of custom blocks to ultimately deliver even greater value with their products.

Rich Morse is Technical MarketingEDA Alliances Manager Laker Custom IC Design Products, SpringSoft Inc. and Mitch Heins is VP of Applications Pyxis Technology Inc.

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