Programming SPARC - Embedded.com

Programming SPARC


Following the prevalence of the SPARC architecture in the world of workstations, the architecture has also begun to gain prominence in the embedded systems applications. Fujitsu's SPARClite family is a collection of SPARC-base microprocessors optimized for use in embedded systems. The SPARClite processor typically consists of a Harvard (Aiken) architecture Integer Unit (IU) core, instruction and data caches, a Bus Interface Unit (BIU), and an In-Circuit Emulator Unit (EMU). The processor also contains special features such as an integer multiply unit, on-chip address decode, DMA channels, and peripheral functions such as timer counters and serial ports.
Due to the wide variety of topics available for embedded SPARC programming, this article shall limit its scope to the discussion of the mechanics of register windows, causes of window-overflow and underflow, and steps required to properly handle the overflow/underflow conditions. The article seeks to help SPARClite users write their application specific trap handlers, including the window-overflow and underflow trap handlers.

ESC_1992_Vol1_Page117_Chu & Huang – Programming SPARC.pdf

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