The MC68300 family and the M68HC16 family are groups of microcontrollers that are designed around a central bus, known as the intermodule bus, upon which independent modules are placed. All of the devices in each particular family have a common CPU, such as the CPU32 for the M68300 family and the CPU16 for the M68HC16 family. There
probably will be upgrades for both CPU cores; however, future cores in a particular family would undoubtedly be able to execute all existing code from prior CPU's in that family.
The peripherals, i.e., timers, serial ports, ND converters, etc., communicate with the CPU via the intermodule bus. There is no direct connection between the CPU and any peripheral other than the intermodule bus. Thus, the peripheral cannot tell what type of CPU is sending instructions over the intermodule bus. As the modules are thus CPU independent, peripherals used on the M68300 family can be used without modification on the MC68HC16
There is a second implication regarding peripheral placement on an intermodule bus structure. Peripherals can be designed with their own local processor, RAM, ROM and I/O structure. The main CPU, i.e., the CPU32 or CPU 16, can communicate with such structures through dual ported RAM. In other words, the intermodule bus opens up a straightforward methodology for implementing distributed processing on a single piece of silicon. While it might be argued by some that peripherals with specialized processor cores and instruction sets are difficult to program, this difficulty is more than offset by the increase in processing throughput gained by off loading repetitive tasks from the CPU to the less complex, intelligent peripherals.
As always integrated circuit manufacturers always are ever conscious about producing new designs in a timely and cost effective manner. The modules, CPU cores and peripherals, can be used on any device that adheres to the intermodule bus concept. New devices can actually be constructed for existing modules by picking the desired CPU core and selected peripherals from a standard library and then using a computer-aided design program to arrange the modules in a “best fit” square and route the intermodule bus between them.