Protecting your low voltage electronic devices from electrical overstress

A common cause of failure for any electronic products is electrical overstress (EOS). While a good instructional manual prevents users from using devices at non-prescribed power levels, unintentional EOS is always possible. Overstress could be an outcome of numerous scenarios, including supply surges and application of overvoltage due to incorrect input supplies. Having effective EOS protection is a primary requirement for product durability.

EOS is used to describe the thermally-induced damage that may occur when an electronic device is subjected to a current (Figure 1 ) or voltage that is beyond the specified limitations of the device (Figure 2 ). The high current that can occur during an EOS event can generate a localized high temperature that causes damage to the materials used in the device’s construction. An EOS event can be a momentary event lasting only milliseconds or can last as long as the conditions persist. EOS can be the result of a single, non-recurring event or the result of ongoing periodic or non-periodic events.
Both EOS and electrostatic discharge (ESD) are voltage overstress conditions, but as shown in Table 1, they differ in the energy involved and time span of the event.

Table 1: Comparison of EOS and ESD.

A typical failure symptom of EOS involves excess supply current being drawn, low resistance between the supply and ground pins, a pin short between either supply and ground, and/or functional failure of devices.

In some failure scenarios, visual damage to the device is evident. This may be in form of bulge or physical hole in component package, burn/discolor/crack in component package. In majority of the cases, the damage may be internal in form of melted/burned metal, melted/open bond wires.

Figure 1: (EOS External Damage)

Figure 2: (EOS Internal Damage)

EOS causes
The primary cause of EOS failure is a voltage surge on the power supply. Overshooting or undershooting during I/O switching, voltage spikes due to internal switching, or an external connection (coupling) can also lead to EOS. Additional designs issues like poor return path due to improper grounding (leading to excessive noise on the ground plane) can lead to EOS of devices. For systems operating in noisy environments, poor shielding can make the system vulnerable to electromagnetic interference (EMI), in turn leading to EOS failures. Devices weakened due to events like ESD will be more susceptible to future EOS events. Latch-up can lead to EOS if the current is not limited or if the event occurs over a long time period. An improper input provided by a user can also lead to EOS on power or I/O lines.

Preventing EOS at the product level
The ideal scenario is to have clean power supplies and controlled ramping at power up and power down. Having proper de-coupling capacitors helps the suppression of any noise on power domains. Additionally, having low resistance conduction paths for power and ground in the printed circuit board help avoid unwanted noise from reaching the device I/O or power lines.

Although the above options help in eliminating the EOS caused due to voltage surge and spikes, the events caused due to reverse voltage, over voltage, and short circuit (over current) are not protected. We will be discussing four protection options (Table 2 ) in this article to cover these scenarios.

Table 2: Comparison of protection methods.

Option #1 – A diode in series on the power line. The main advantage of this circuit is that it is low cost and requires less board real estate. It can protect the systems from reverse voltages by disconnecting the reverse voltage input applied on the system. The voltage value up to which the diode can protect is equal to the reverse break down voltage parameter of the diode.

The main disadvantage of this circuit is that there will be a series voltage drop equivalent to the forward voltage drop parameter of the diode used. It also cannot protect the device from over voltage and short circuit/over current conditions.

Option #2 – A Bridge rectifier consisting of 4 diodes. The main advantage of this circuit is that it not only protects the systems from reverse voltage inputs but also enables the system to operate even with a reverse input voltage. The voltage value up to which the diode can protect is equal to twice the reverse break down voltage of the diode.

However, there are some disadvantages to this circuit. It cannot protect the device from over voltage and short circuit/over current conditions. There will be a series voltage drop equal to twice the forward voltage drop parameter of the diode if the diodes. Also, this circuit consists of bulky diodes which will consume board space and add to system cost.

Option #3 – A combination of a Zener diode and resettable fuse. This circuit consists of a series element; i.e. resettable fuse and a parallel element Zener diode. The series element limits the current and the parallel element clamps the voltage level. The resettable fuse disconnects or breaks when the there is a surge of large current passing through the fuse.

Resettable fuses are made up of conductive polymer and the working principal of these resettable fuses is that when the temperature of the device (i.e. the fuse temperature) crosses the threshold limit, they break temporarily. They switch back on when the temperature drops below the threshold (Figure 3 ).

Figure 3: Variation of PTC resistance with Temperature

When an input voltage exceeds the Zener diode breakdown voltage parameter, there is a sudden surge in current through the Zener diode and also in the resettable fuse. The increase in the temperature of the fuse causes the fuse to break the circuit; i.e. resistance of the fuse will increase many fold, which is equivalent to the circuit being open. When the over voltage condition is removed, the current stops flowing through the fuse and the temperature of the fuse reduces, thus closing/completing the circuit again after some time. Figure 4 shows the variation of the current and resistance with time during faulty conditions.

When a reverse voltage is applied at the input, the Zener diode will be forward biased. There will a large surge of current through the PTC fuse leading to an increase in temperature of fuse, and hence the circuit breaks.

During an over current or short circuit scenario, the current through the fuse increases, this increasing the temperature and in-turn the circuit breaks, thereby protecting the system or device.

The main advantage of this circuit is that it can protect the devices/systems from all EOS scenarios – over-voltage, reverse voltage, short circuit or over current. Only two components are added to the BOM/cost.


Figure 4: Variation of the current and resistance with Time during Fault conditions (source Digikey)

The main disadvantage is that there will be a series of voltage drops because of the resistance of the resettable fuse. Even though the initial resistance of resettable fuse may be less, the resistance of the resettable fuse increases with temperature and the number of times the fuse gets reset. This series voltage drop depends on the current consumed by the system being protected; i.e., the drop increases with increase in systems current consumption (V=IR).

Another disadvantage of this circuit is that there is tremendous increase in temperature on the order of 90°C. So, we cannot keep other devices near this circuit, therefore increasing the effective board area used by this circuit. There is a similar device called a Polyzen device that has both a resettable fuse and Zener diode on a single component, thus occupying limited space on the board. However, we will still have a series voltage drop due to this device.

The two main parameters of a resettable fuse are the ‘Ihold’ current and the series resistor. The ‘Ihold’ current is the current up to which the fuse will not break. This current value must be equal to or slightly more than the systems maximum current consumption. To keep the series voltage drop across the fuse minimum, a fuse having the least series resistance has to be chosen.

A Zener diode should be chosen such that the breakdown voltage of the Zener diode is equal to or slightly more than the working voltage of the system being protected. However, the break down voltage should not exceed the maximum voltage limit of the system being protected.Option #4 – MOSFET-based protection circuit. As discussed theprimary disadvantage of the above three protection circuits are thevoltage drop cased by the protection components and thermal dissipation.A MOSFET-based circuit help eliminate these voltage and thermal losseswhile providing effective protection. Due to negligible voltage drop,this protection can even protect analog pins used to sample/monitor anexternal voltage.

An ideal overvoltage protection circuit needsto satisfy two criteria. The first is to prevent over or reverse voltageto be applied to the device pins. The second is to not to intrude onthe normal function of the circuit (i.e to avoid any series voltagedrop).

Consider an IC that can be operated from 1.71V to 5.5V.Such devices typically get damaged if a voltage above 6V is applied.Thus, the protection circuit must pass all the working voltages (1.71Vto 5.5V) without any voltage drop. The protection circuit must alsocut-off the supply to the microcontroller when the applied voltage isgreater than 5.5V.

The main disadvantage of the circuit is thatthere are six components in the circuit and this circuit does notprotect form over current (short circuit) EOS scenarios.

The functional block diagram of the protection circuit is shown in Figure 5 .The first block is just an enhancement mode P-MOS which does not allowthe reverse polarity input to pass to the next voltage check block. Thevoltage check block consists of a Zener Diode and a PMOS to control theswitch.

Figure 5: Functional block diagram of the circuit

Theprotection circuit consists of two P-channel MOSFETs (Figure 6) on thepower line allowing the power/current to flow from input to outputdepending on the voltages applied to the line. The protection circuitwill protect from a maximum over-voltage or reverse-voltage of 12 Volts(max of Q1VDG). The cut-off voltage on the 5-V line is 5.7 V and on the3.3-V line is 3.6 V. This means, if you apply more than this voltagelevel, the P-MOS Q5 will turn off, thus protecting the device. Thecurrent consumption of these protection circuits is less than 6 mA.

Figure 6: Schematics of the 5V and 3.3V protection circuit s

Considerthe 3.3V protection circuit. When the external voltage is between 1.8 Vand 3.3 V, the P-MOS Q4 conducts because the voltage on the gateterminal is less than VTH with respect to drain (P-MOS will switch offif the voltage on the gate terminal is more than VTH with respect toDrain). When the external power supply exceeds 3.3 V, the P-MOS Q5starts conducting. This eventually turns off P-MOS Q6 at 3.6 V,protecting the device from over-voltage. When a reverse voltage isapplied across the protection circuit from an external source, Q4 P-MOSwill turn off, thus protecting the device from reverse voltage. Thecircuit behaves as a bidirectional protection circuit i.e. it allows anyvoltage from the device to pass to the external world, where as limitsthe voltage that is entering the device.

The selection of a PMOSdevice depends on three main requirements: the minimum input voltagethat the circuit has to pass, the maximum input voltage that theprotection circuit has to withstand, and the series voltage drop acrossthe protection circuit. Suppose the minimum input voltage of the deviceis 1.8V and maximum input voltage up to which the circuit has to protectis 10V. The PMOS device selected should have VTH less than 1.8V and theMaximum VDG should be more than 10V. To keep the series voltage dropacross the protection circuit to a minimum, the on resistance RDS of thePMOS device has to be as low as possible.

The selection of the series resistor R4 and Zener diode combination (Figure 7 )depends on the cut-off voltage at which the protection circuit blocksthe external input voltage. When the input voltage is increased to theZener break down voltage (Vz), the voltage across the resistor R4 willbe nearly zero as Zener will not be conducting ideally. When the inputvoltage is more than Vz volts, the voltage across resistor R4 startsincreasing. When the voltage across the R4 reaches Vth of Q5-PMOS, theQ5 PMOS switches ON, thereby increasing the voltage across R5. Thismakes the Q6 P-MOS turn off, thus breaking the connection from theexternal input. Therefore, the Zener diode breakdown voltage and the Vthof the PMOS determine the voltage at which the external voltage is cutoff; i.e., VCUT-OFF = VZ + VTH.

Say we need the protectioncircuit to cut-off at 5.6V Then VZ= VCUT-OFF – VTH. Considering a P-MOSwith a VTH voltage of 1.8V, we have VZ as 5.6V-1.8V= 3.8V. Thecombination of resistor R4 and Zener should be such that when anexternal input of 5.6V is applied, the voltage across VZ has to be 3.8V.Since the Zener diode is not ideal, we need to choose a Zener diodethat has VZ greater than 3.8V like 4V or 4.3V. To determine anapproximate value of resistor, we read the V-I curve of the Zener diodeand check what the current passing through the Zener is when the voltageacross the Zener diode is 3.8V. If it is 1mA when the voltage acrossthe diode is 3.8V, then the maximum resistor value of R4 is =(5.6V-3.8V)/1mA = 1.8k. A good practice for choosing resistor R4 is touse a variable resistor and Zener combination and tune the resistor toget a required cut-off voltage.


Figure 7: V-I curve of the Zener diode (source diode datasheet)

Conclusion
Theabove circuits were tested for the accuracy in field operation and werefound to be successful in protecting the device form over voltage,reverse voltage and over current scenarios for devices working at 3.Vand 5V. Following are the basic comparison of the protection circuits toenable user in selecting an ideal protection for their design.

Pavankumar Banakar is a Systems Engineer Senior in Development Kits Team of CypressSemiconductor, Bangalore since 2011. He has couple of years of industryexperience in Embedded System Development and System Validation. Hecompleted his Bachelor of Engineering from R.V College of Engineering,Bangalore, India. He can be reached at .

Rinku P Mathew is a Systems Engineer Senior at Cypress Semiconductor with eight yearsof industry experience with microcontrollers and embeddedapplications He is currently pursuing his MS from Manipal University,Bangalore, India. You can reach Rinku at rinku.mathew@cypress.com .

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