PSoC 6 is Purpose-Built for the IoT -

PSoC 6 is Purpose-Built for the IoT


The Internet of Things (IoT) is rapidly evolving. It's not so long ago that the term “IoT Device” made you immediately think of something with an 8-bit microcontroller (MCU) that consumed relatively power and offered relatively little performance. How things have changed…

Rather than have “dumb” IoT devices capturing raw data and passing this data “up-the-chain” for processing, there's an increasing trend to perform “processing on the edge.” This means that the IoT device pre-processes the raw data, boils it down, and packages it up into useful information that it then hands-off to higher-level systems.

Unfortunately, as the devices on the edge become increasingly intelligent, they provide more attack vectors into the system. Thus, in addition to processing on the edge, there is also a trend toward security on the edge.

Last but not least, while many IoT devices employ wired connections to other systems and the Internet and Cloud, there's also an increasing trend toward wireless solutions.

Programmable System-on-Chip (PSoC) devices from Cypress Semiconductor boast a sophisticated mixture of programmable analog fabric and programmable digital fabric augmented with a hard MCU core and hard peripheral cores.

In order to address the IoT requirements noted above, the folks at Cypress Semiconductor have just announced the PSoC 6, which they describe as being “Purpose-Built for the IoT.” The PSoC 6 is the first PSoC family to support dual, heterogeneous processors — a 32-bit ARM Cortex-M4 running at up to 150-MHz and a 32-bit ARM Cortex-M0+ running at up to 100-MHz, all supported by 1MB of Flash and 288KB of RAM.

PSoC 6 dual-core MCU architecture example (Source: Cypress)

Cypress' proprietary ultra-low-power 40-nm SONOS process technology enables the PSoC 6 MCU architecture to feature industry-leading power consumption with 22 µA/MHz and 15 µA/MHz of active power on the Cortex-M4 and Cortex-M0+ cores, respectively. With dynamic voltage and frequency scaling (DVFS), the PSoC 6 MCU architecture offers both performance- and power-critical processing capability. The dual-core architecture enables power-optimized system design where the auxiliary core can be used as an offload engine for power efficiency, allowing the main core to sleep.

Software-defined peripherals can be used to create custom analog front-ends (AFEs) and digital interfaces for a wide variety of system components such as electronic-ink displays. The PSoC 6 architecture also offers flexible wireless connectivity options, including fully integrated Bluetooth Low Energy (BLE) 5.0. Furthermore, the PSoC 6 features the latest generation of Cypress’ capacitive-sensing technology, CapSense, enabling modern touch and gesture-based interfaces.

The PSoC 6 can be evaluated using the BLE Pioneer Kit (CY8CKIT-062-BLE), which costs $75. Furthermore, this kit can be augmented with the E-ink Display Shield (CY8CKIT-028-EPD) for an additional $20.

BLE Pioneer Kit (Source: Cypress)

BLE Pioneer Kit with E-ink Display Shield (Source: Cypress)

With regard to security, the PSoC 6 MCU architecture provides a hardware-based Trusted Execution Environment (TEE) with secure boot capability and integrated secure data storage to protect firmware, applications, and secure assets such as cryptographic keys. PSoC 6 implements a broad set of industry-standard symmetric and asymmetric cryptographic algorithms, including Elliptical-Curve Cryptography (ECC), Advanced Encryption Standard (AES), and Secure Hash Algorithms (SHA 1,2,3) in an integrated hardware coprocessor designed to offload compute-intensive tasks. The architecture supports multiple, simultaneous secure environments without the need for external memories or secure elements, and offers scalable secure memory for multiple, independent user-defined security policies.

More information on the PSoC 6 MCU architecture and access to the PSoC 6 Early Adopter Community is available at

5 thoughts on “PSoC 6 is Purpose-Built for the IoT

  1. “From the first diagram, it appears that each PSoC has its own set of peripherals. Only some timers (undefined here), Flash and SRAM and IPC are shared. I presume that “IPC” stands for “Inter Process Communication”, so there is a dedicated resource for

    Log in to Reply
  2. “Good questions. It will be really interesting to see how they handle the two cores, especially for debugging. It's hard enough debugging one CPU at a time. I hope they've given enough thought to the tools for this.”

    Log in to Reply

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.