PWI 2.0 spec provides enhanced two-wire SoC interconnect -

PWI 2.0 spec provides enhanced two-wire SoC interconnect


National Semiconductor and ARM have jointly developed the second-generation PowerWise interface (PWI) specification, which provides enhanced power-management interconnect capability to advanced system-on-chips (SoCs) in battery-powered devices. As an extension of PWI 1.0, the new spec adds multi-domain capability to address emerging needs of highly integrated SoCs.

To extend battery life in handhelds with increased functionality, device makers require advanced power management techniques to dynamically optimize the power consumption of each individual function inside a feature-rich SoC. Other vendors that helped craft the new standard include Matsushita, Philips, Samsung, and STMicroelectronics.

The original PowerWise interface specification defines a two-wire serial bus connecting SoCs with PMICs. The interface provides master-to-slave communication, which is optimized for control of a voltage regulation system that enables system designers to dynamically adjust the supply and back-bias voltages on digital processors.

The PWI 2.0 specification maintains the low-power, low-latency, high-bandwidth capabilities of release 1.0, while providing flexibility with an increased PMIC register addressing space, expanded command set and provisions for a multi-point bus with two masters and up to 16 logical PMIC slave connections on one or more PMIC devices.

The PWI 2.0 specification is royalty- and license-free. To adopt the specification, download and submit the agreement at

National Semiconductor is expected to launch PWI 2.0 specification-compliant external power management integrated circuits in the second half of this year. For more information, go to or

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