Quad SerDes integrates clock jitter cleaner - Embedded.com

Quad SerDes integrates clock jitter cleaner

Dallas, Tex.—Texas Instruments (TI) is offering a four-channel SerDes chip that enables high-speed, bi-directional, point-to-point data transmission with up to 30-Gbit/s.

The device has the flexibility to be configured either as a XAUI or 10 GFC transceiver. This multi-rate transceiver supports a wide data bandwidth range from 600-Mbit/s to 3.75 Gbit/s per serial lane to address design challenges in a variety of applications such as gigabit Ethernet links or backplane and front plane connections.

The TLK3134 performs the parallel-to-serial, serial-to-parallel conversion and clock extraction functions for a physical layer interface, all in one compact device. The integrated reference clock jitter cleaner eases the design process and allows the use of an economical reference clock source.

The device meets the CPRI and OBSAI specifications for wireless infrastructure equipment. The backplane reach and transmission distance over cable can be extended by this SerDes' serial side transmit de-emphasis and adaptive receiver equalization.

Pricing: $35 each in 1,000-unit quantities.
Availability: Now in a 289-pin BGA package.
Datasheet: Click here.

Texas Instruments, www.ti.com

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