CMOS technology enables a single FPGA device to have many I/Ointerfaces. Recently, low power has emerged as a principal theme inhigh-speed I/O interfaces, and voltage reduction offers the mosteffective means of minimizing power consumption.
As a result, the noise margin of these I/O interfaces has becomesmaller. Thus, it is essential for FPGA users to quantify system-levelsimultaneous switching noise (SSN) in a chip/package/PCB environment.This article offers a systematic SSN overview with the focus on SSNcaused by FPGA output buffers.
This noise is widely known as simultaneous switching output noise(SSO), and is differentiated from the SSN caused by input buffers. Adescription of the causes of system-level SSO is presented, and ahierarchical system-level SSO modeling methodology is proposed. Aprocedure for correlating the SSO models to frequency- and time-domainmeasurements is provided and several PCB design methodologies forminimizing SSO in PCBs are offered.
An FPGA-mounted PCB is a complex system that can be divided into thedie, which contains active circuits; the package, which supportsrouting with embedded passives; and the board, which provides theconnection between the FPGA and the outside world. It is difficult tocharacterize noises inside the chip for this type of system.
Thus, it is valuable to quantify SSO at either near- or far-ends ofPCB traces connected to the FPGA. Two primary factors contribute toSSO: power distribution network (PDN) impedance and mutual inductivecoupling among switching I/Os.
The Power Distribution Network
From a systematic perspective, a PDN consists of die-, package- andboard-level components, which together supply power to the CMOScircuits. When a number of CMOS output drivers switch on at the sametime, a substantial number of currents switch rapidly in the inductivecircuit component of the PDN. This rapid switching generates a delta-Ivoltage drop.
These inductive parasitics are due to the interconnectionstructures, such as the power balls of a BGA package and power vias ina PCB. Furthermore, the switching current source excites radialelectromagnetic waves in a power/ground plane pair. These waves reflectfrom the edges of the planes, causing resonance in the plane cavity andresulting in voltage fluctuations.
|Figure1: Shown is a schematic representation of SSO model for a FPGA-mountedPCB.|
Mutual inductive coupling
Another important factor is the mutual inductive coupling, especiallyaround the package/PCB interfaces. The BGA package balls and the PCB'svias are a tightly coupled multiconductor structure.
Each I/O ball and its corresponding PCB via form a closed loop withthe nearest ground ball and ground via. When multiple I/Os togglesimultaneously, it causes I/ O transient currents to flow along thesignal loops. These I/O transient currents create time-varying magneticfields, which penetrate into neighboring signal loops and inducevoltage noise.
A good SSO model should represent the basic cause mechanisms. Figure1 above shows a hierarchical model for predicting SSO in a PCB. At thedie-level, output buffer models are required to provide accuratecurrent profiles on the supply rails and signal lines with limitedcomplexity.
At the package-level, a PDN model and a signal coupling model can beindividually extracted from modeling tools for simplicity. Theinteraction effect between the PDN and signal coupling model should becarefully considered. These two models act as a bridge connectingoutput buffer models at the package bump side to PCB-level models atthe package ball side.
A PCB's PDN model typically contains power/ground planes and mountedbulk/decoupling capacitors, while the PCB's signal coupling modelconsists of a tightly coupled via array and loosely coupled signaltraces on different signal layers.
The interaction between these two PCB-level models occurs inside thePCB via array, where the inductive crosstalk introduces noise into thePDN model and the delta-I noise inversely degrades I/O signal quality.This hierarchical modeling methodology reasonably preserves simulationaccuracy and concurrently improves computational efficiency for such acomplex system.
|Figure2: A signal loop of t x d in size consists of a signal via and anearest ground via.|
There are two basic design methodologies for mitigating SSO inFPGA-mounted printed circuit boards based on the SSO cause mechanisms:
Design for minimizing inductive coupling. Simulation results showthat the inductive coupling in the package/PCB interface results in thehigh-frequency spikes on the SSO waveform. A signal loop of t x d insize consists of a signal via and a nearest ground via.
This loop measures inductive coupling, as shown in Figure 2 above. For a largeraggressor I/O loop, its magnetic fields more easily invade nearbyvictim loops. The larger a victim I/O's signal loop, the morevulnerable it is to attack by other aggressor I/Os.
Thus, to reduce crosstalk and the parameter t, the design should usea thinner PCB, and critical I/Os should be bonded out on shallowersignal layers. A design can also shorten the distance d between I/Ovias and ground vias to reduce crosstalk. In this design, a couple ofI/O pads are intentionally hardwired to the ground planes and the VCCIOplane for reducing the signal loop size of aggressor and victim pins.
|Figure3: Shown is a pin map of I/O Bank 1 and 2.|
This test performed two measurements on FPGA I/O Bank 1 and 2,respectively, as shown in Figure 3above , to evaluate the effectivenessof this methodology. All I/Os in the two banks are configured as aLVTTL 2.5V interface with 12mA current strength. The I/Os areterminated with 10pF capacitors through 50 ohm striplines.
In Bank 1, Pin AF30 is the victim pin. Six pins (W24, W29, AC25,AC32, AE31 and AH31) are programmed to the logic “0” node in the FPGAdesign pattern. These pins are hardwired to the PCB ground planesthrough vias. Five pins (U28, AA24, AA26, AE28 and AE30) are programmedto the logic “1” node and are hardwired to the VCCIO plane in the PCB.The other 68 I/Os act as aggressors toggling simultaneously at 10MHz.
In Bank 2, there are no hardwired I/Os acting as programmable groundand VCCIO pins. However, 11 I/Os (E31, H28, H30, H31, K25, K32, M24,M26, P24, P29 and T28) are unused and the other 68 I/Os switchsimultaneously for a fair comparison with Bank 1, as shown in Figure 3.
Bench measurements show that the ground bounce at AF30 in Bank 1 islower by 17 percent than that at G30 in Bank 2, and the power sag islower by 13 percent. Simulation results also verify this improvement.The mitigation in SSO numbers is expected because the appearance ofprogrammable ground pins reduces the distance d of aggressor and victimloops, as illustrated in Figure 2. However, the improvement is limitedbecause the signal loop size inside the package cannot be reduced.
An effective decoupling strategy and a thinner power/ground planepair decrease this input impedance. However, shortening the length ofpower vias connecting VCCIO balls to the VCCIO plane is the mostefficient way to decrease input impedance.
The CST-MWS simulationresults verify this point. Moreover, a short power via forms a smallerloop with its nearest ground vias, and this loop becomes lessvulnerable to be attacked by toggling aggressor I/Os.
Therefore, the VCCIO plane should be placed closer to the top layerin the PCB stack-up. A comprehensive analysis of simultaneous switchingnoise in an FPGA-mounted PCB has been presented. First, the analysisindicates that two important cause mechanisms of SSO are the crosstalkin the package/PCB interface, and the PDN impedance profile of packageand PCB.
The correlated models can be applied to guide better PCB design formitigating SSO. Several methodologies for reducing SSO were covered.Among them, reasonable signal layer assignment and the implementationof programmable ground/power pins help minimize the PCB-level inductivecrosstalk, and using a shallow position for the VCCIO layer in the PCBstack-up reduces the PDN impedance.
Geing Liu is Technical Staff Member, Characterization Group,Product Engineering; Hong Shi is Manager, Packaging Design Engineering;Alan Chang is Senior Product Engineer; and San Wong is Senior Manager,Product Engineering, at Altera Corp..