RCF device combines with DSP to ease baseband processing - Embedded.com

RCF device combines with DSP to ease baseband processing

PARIS, France — Motorola's MRC6011 Reconfigurable Compute Fabric (RCF) device and MSC8126 multicore StarCore digital signal processor (DSP) can be used with the company's wireless application software library modules for use in baseband processing for 3G and broadband wireless access systems.

The MRC6011 RCF device is designed to enable system designers to adapt algorithms and fix bugs before and after deployment, fine-tune baseband architecture and manage partition and load on the fly, design multi-standard wireless platforms, and add advanced capabilities, such as adaptive antenna and multi-user detection.

The MRC6011 combines six RCF cores into a homogeneous compute node capable of operating at 250MHz, with a 100MHz maximum operating frequency for off-core buses. The six-core MRC6011 device is designed to deliver a peak performance of 24 giga multiply-accumulates per second (GMACS). At 4-bit resolution, the device is capable of performing at 48 giga complex correlations per second.

It is a system-on-chip device that comprises two identical and scalable reconfigurable compute (RC) modules. There are three identical RCF cores per module, and each core has a 16-element processing array. The RC controller is an optimized RISC processor designed for efficient C code compilation, and it features instruction and data caches, programmable timers and external general-purpose output lines. Core peripherals include large high-speed buffers, a special-purpose complex correlation unit, and a single- and burst-transfer DMA controller.

The MRC6011 is manufactured on 0.13-micron CMOS process technology, enabling an internal logic voltage of 1.2V and input/output voltage of 3.3V. Typical power consumption is targeted at less than 3W. The device is in a 31mm x 31mm tape ball grid array (TBGA) package.

The MSC8126 is the first in a family of multicore StarCore DSPs and combines four StarCore DSP cores, a turbo coprocessor, a Viterbi coprocessor, a universal asynchronous receiver/transmitter, four time-division multiplexed serial interfaces, 32 general-purpose timers, a flexible system interface unit, an Ethernet interface, and a 16-channel DMA engine that handles independent data transfers.

The four extended cores are designed to deliver up to 6400 million multiply-accumulates per second of DSP performance at 400MHz. The four-core MSC8126 device is planned to be available at two core speeds: 350MHz and 400MHz.

Motorola plans to release a library of application software modules for both the MRC6011 and MDC8126 devices. The first version of the library is targeted at Universal Mobile Telecommunications System applications with both chip-rate and symbol rate modules and come as C-callable modules.

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