Over the last decade a fundamental shift has occurred in system-on-chip (SoC) design. This shift has largely gone unnoticed and has introduced significant unnecessary costs and inefficiencies into the design process – costs that must be eliminated if SoC design is to remain viable for a wide range of companies.
In the past, most of the design effort in an SoC was centered on creating unique new logic that differentiated the design from other designs available. It has been this understanding of SoC design that drove the evolution of design tools and technologies over the past decade – the focus on new logic creation.
Fast-forward to today and we find a very different situation, with SoCs that contain large amounts of internal and third-party intellectual property (IP) integrated into complex systems. With this change, much of the design effort is now spent on integration, verification, and software development, with little in the way of tools and technologies to automate this integration.
The changing role of IP
Fueling this change has been the rise of IP. For years IP and design reuse were talked about but rarely practiced. However, thanks to higher-capacity design tools and larger SoC designs, designers can now treat IP as large pieces of design that not long ago would have been standalone chips. Good examples of this trend are complex standard interfaces such as the latest iterations of USB, PCI-Express, and Ethernet.
These interfaces, which are a baseline requirement for many designs, are not seen as differentiated value, are complex to design from scratch, and have well-defined interfaces both internally and externally. And it is these very characteristics that make them perfect candidates for IP reuse. The result is that most of a typical SoC design today is made up of external IP and internal design reuse.
Figure 1: Anatomy of an example SoC
In an ideal world, building this type of design would involve selecting the interfaces and subsystems needed, connecting them together like Lego blocks, and having a system that works immediately. Unfortunately this is virtually never the case, as any experienced designer will attest. There are two data points that illustrate the issue: 1) for every dollar spent in IP acquisition, two to three dollars are spent on integration; and 2) in 65nm designs, up to a quarter of the hardware design budget is spent on qualification of IP.
In addition to these costs, poor IP choices early in a project can lead to large cost increases for late-stage system optimizations. For example, it may be discovered late in the design process that a poor IP choice puts a larger-than-expected load on the embedded processing subsystem. This means the design team must perform significant software optimizations to meet the performance goals, potentially adding cost, risk, and project delay.
What drives these IP-related costs? Two main factors:
Factor #1: IP typically is created or selected as a standalone component on a purely functional basis. “How well does this IP deliver the specific function that is needed, and is it cheaper to buy the IP or build it from scratch?” While these are important aspects of IP selection, they ignore the cost implications of how well the IP fits into both the SoC and the design environment.
Questions such as “How will this IP impact my verification, software design, and system integration?” go unanswered. Worse yet, much of the increase in verification and software complexity is driven by poor visibility into the IP environment, meaning that significant re-verification is needed at the system level, where it is far more complex. Likewise significant software reverse engineering and optimization are required to fully utilize the underlying IP.
Factor #2: Inconsistent IP quality. This includes not only functional bugs, but all aspects of IP deliverables that affect usability spanning technical, business, and support issues. A lack of consistent quality in any of these areas means design teams must re-qualify IP before it can be used in a design, something that is expensive and time consuming.
Some of the key considerations for the qualification are:
1) Quality: Can the IP supplier deliver the full package of functionality and support both today and in the future?
2) Compatibility: Will all my IP work well together in the context of the larger system?
3) Capability: Does the IP have the flexibility needed for today’s design and future derivatives?
4) Fit: Does the IP have the necessary infrastructure to be utilized in the existing design environment, and can I take advantage of advanced methodologies?
Given the complexity of IP qualification and the potential costs imposed by a bad IP choice, experienced designers often constrain their IP alternatives to those that fit within an acceptable risk profile and are from companies they have used before – even if that IP is not an ideal fit for their design.
But such constraints typically do not address the broader issues of IP quality mentioned above, and significant costs still crop up while integrating the IP into the design. Furthermore, the self-imposed limits to IP selection significantly restrict the tradeoffs that can be made to determine the best overall system implementation, can impact differentiation, and can lead to even greater costs later on.
A new approach to IP is neede, one that looks beyond the raw functionality of IP components to optimize the process of integrating them into the system. The traditional notion of IP integration must be expanded; IP must be integrated across functional boundaries and delivered as a single seamless entity.
With this new approach, designers will utilize tools and technologies that leverage the capabilities of this new class of IP to rapidly bring together designs, thus eliminating excessive qualification and integration costs mentioned previously.
An open integration platform that supports this approach would reduce design cost while also making it easier to compare and contrast different IP choices – which in turn would make it easier to create uniquely differentiated designs.
Figure 2: An open integration environment enabled by integration-optimized IP
Integration-optimized IP must redefine what it means to deliver IP by addressing four key requirements:
1) Remove the need for qualification by having a predictable level of quality across IP from different suppliers, a consistent and well-defined set of deliverables, and a comprehensive support infrastructure – all backed by silicon-proven data.
2) Extend the scope of interface IP in particular to span from the physical interface all the way up to the driver layer. The driver layer is critical since it is how applications are able to take advantage of the underlying IP.
Looking further ahead, this scope should be able to expand even further to deliver IP subsystems that bring together multiple interfaces and local interconnect and make them available as a single IP deliverable.
3) Optimize IP deliverables to ensure that they are easily integrated into the design with consistent, well-defined interfaces, comprehensive design databases, reference flows, and reference implementations.
Specific attention needs to be paid to the verification and software environments. For example, integration-optimized IP must provide not just a reusable verification environment, but also a complete test plan and set of metrics that allow the integrator to eliminate unnecessary verification activities.
4) Provide a way of encapsulating IP so that different IP solutions can be compared in the context of the target design before the project commits to a final system architecture.
Design teams often need to be able to trade off different IP options to get the best system implementation for a particular application. For instance, an IP component that works well in a high-performance router may be inappropriate for low-cost embedded devices. Beyond technical tradeoffs, teams also need to perform economic analysis of IP choices.
For example, it may be cheaper in the overall project perspective to accept an expensive, high-performance I/O subsystem rather than performing costly design optimizations to avoid it. Performing these tradeoffs requires both consistency in the IP offerings and a choice of different IP implementations.
The open IP ecosystem
Delivering choice requires an open ecosystem approach to IP, as no single company can be everything to everyone. As Cadence develops and delivers integration-optimized IP stacks, beginning with the SuperSpeed USB 3.0 offering, component IP is utilized from internal sources as well as from suppliers across the IP industry. There is an inherent understanding of the importance of these partnerships in giving customers the choice they need.
Working with the industry, Cadence is defining a consistent set of deliverables for the underlying component IP, such as PHY, SERDES, controllers, and others. In addition, Cadence integrates component IP, performs cross-functional optimizations, builds a comprehensive hardware/software compliance test environment to help ensure quality, and, finally, delivers a fully integrated stack that has been optimized for integration into customer designs.
The value of integration optimization
To illustrate the benefits offered by integration-optimized IP let us review what Cadence experienced in creating the optimized SuperSpeed USB 3.0 stack. The stack is comprised of component IP from both suppliers and internal sources – all of which had been silicon-proven to be high quality.
Figure 3: Cadence integration-optimized USB 3.0 IP stack
During the process of integrating the stack, Cadence engineering teams encountered many of the same problems customers experience in their own integration activities: inconsistent tool flows, inconsistent design databases, incomplete data, and others. Furthermore, testing the raw integration exposed inconsistencies and inefficiencies in the interfaces between IP components as they interacted in ways that had not been exercised previously.
Integration of the stack consumed about 47 headcount-weeks of work, which is consistent with customer data from similar projects. This excludes the additional effort Cadence applied to make the IP environment scalable and reusable across a wide range of designs.
So how does the integration-optimized SuperSpeed USB 3.0 IP stack compare with the component IP stack?
1) Overall quality is improved and can be independently validated by customers thanks to the comprehensive hardware/software verification and qualification environment provided with the IP.
2) Cadence found the effort required to integrate the interface into a new design has been reduced at least 50 percent (and in many cases much more) by utilizing a common mixed-signal design environment and a complete reference implementation.
3) Based upon internal testing, performance has been improved by a factor of 10 compared to the component IP stack, with greater than 360 MB/s read performance in the USB 3.0 device configuration.
4) Dynamic and leakage power was also significantly reduced though front-to-back power optimization enabled by a Common Power Format (CPF)-based mixed-signal implementation flow for both the PHY and controller.
It is worth noting that the performance improvement was only possible through cross-functional optimization from the driver into the controller – something that would typically not be possible for an IP customer, without a detailed working knowledge of the IP and the ability to modify it, or for a software developer using a generic USB stack. This illustrates the importance of integrating and optimizing IP in a holistic manner.
This example shows the benefits of integration optimization for a single IP component. The impact is even more significant when these improvements accrue across multiple IP components in a design. For example, when the quality of the IP is known to be good, teams can focus verification efforts in a more strategic way, saving significant resources. When IP is supplied with an optimized software layer, more effort can be applied to application development and not squandered on low-level optimizations.
The way forward
Delivering this new class of IP is not easy and requires a commitment from the IP providers as well as IP users. If IP continues to be judged purely at a functional level, there will be little incentive for IP providers to make the necessary investments.
The rewards that come with a successful transition to integration-optimized IP however are significant; the savings are more than could be achieved by any point optimization of the SoC design process.
Moving the industry towards integration-optimized IP will enable SoC design teams to once again put the majority of their focus on the task of creating unique design differentiation and help drive innovation into new product development.
(Neil Hand is Group Director, Product Marketing at Cadence Design Systems, Inc. and is focused on the challenges of SoC Realization and Integration-optimized IP. With 19 years of experience, he has worked with a number of leading EDA companies in the design and verification space, including Cadence, Mentor/0-In, Averant, Get2Chip and Synopsys. Prior to that he was a telecommunications systems design expert at Ericsson. He holds a Bachelor of Electrical Engineering degree and Bachelor of Science Computing degree from the Queensland University of Technology, Australia.)