Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework

Many applications employ a mix of algorithms that require both sequential and parallel processing. Previous research has found that a heterogeneous computing system can reduce computation time by partitioning algorithms to processing units (CPU, GPU, or FPGA) best suited for the particular workload. System-on-Chips from Xilinx and Altera with both FPGA fabric and ARM processors on a single die show promise in accelerating applications like cognitive radio that utilize both parallel and sequential processing but have tight timing requirements.

This paper presents the design of CRASH: Cognitive Radio Accelerated with Software and Hardware, a framework that addresses these challenges on Xilinx’s Zynq SoC. CRASH provides the capability to partition designs between processing blocks in the FPGA fabric and user programs running in Linux on the ARM processors.

CRASH targets accelerating the key enabling functions of cognitive radio, an emerging ?eld concerned with alleviating the congested wireless spectrum by using alternate licensed frequencies. Since most cognitive radio functions, including spectrum sensing and spectrum decision, are implanted in soft- ware, inherent parallel structures that exist in their execution chains can be easily exploited on FPGAs.

Faster spectrum sensing allows the cognitive radio to react quickly to changing spectrum availability. Also, spectrum decision algorithms must have a fast response time to prevent adverse interference with licensed users. The CRASH framework on the Xilinx Zynq SoC enables effective implementation of both these kinds of processing.

We implement spectrum sensing and the spectrum decision in three con?gurations: both algorithms in the FPGA, both in software only, and spectrum sensing on the FPGA and spectrum decision on the CPU. We measure the end-to-end latency to detect and acquire unoccupied spectrum for these con?gurations. Results show that CRASH can successfully partition algorithms between FPGA and CPU and reduce processing latency.

To read more of this external content in PDF form, download the complete paper on line from the author archives at Northeastern.

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