Reference design supports memory-intensive AI workloads -

Reference design supports memory-intensive AI workloads


Lattice Semiconductor Corp. and Etron Technology Inc. have released a memory controller reference  design for Etron’s low-pin-count RPC DRAM for low-power edge AI and video-processing applications that require a compact form factor. Lattice’s low-power ECP5 FPGA, as the memory controller for the RPC DRAM, provides the processing for the AI or smart-vision workload. Applications include industrial cameras, drones, AR/VR systems, and advanced driver-assistance systems (ADAS).

The reference design addresses the requirements for lower power consumption, smaller form factor size, and reduced data latency. One of the challenges is that smart vision and other AI applications generate a lot of data that is typically uploaded to the cloud for analysis, said Lattice, but due to concerns over data latency and privacy by edge device OEMs, they want to handle more of that analysis locally without additional power or size to their design.

The reference design uses 15% less power than a system using standard DDR3 DRAM, with an overall design footprint smaller than a 9 × 13-mm BGA packaging used by a standard DDR3 DRAM chip. Another advantage of the solution is that it doesn’t require expertise in FPGA-based design thanks to Lattice’s design tools and sensAI software stack, said Lattice’s director of strategic alliances, Kambiz Khalilian.

Lattice also recently released the latest version of its solutions stack for on-device AI processing at the edge, Lattice sensAI 3.0. Addressing data security, data latency, and privacy issues, the new sensAI 3.0 solutions stack doubles the performance and cuts power consumption in half for edge AI applications, said Lattice. It includes support for the CrossLink-NX FPGAs for low-power smart-vision applications. It features customized convolutional neural network (CNN) IP, an accelerator IP that simplifies implementation of common CNN networks and is optimized to further leverage the parallel processing capabilities of FPGAs.

The Lattice/Etron reference design includes software development tools, featuring a GUI-based memory code generator tool and a Verilog simulation model. Application demonstrations using the Lattice sensAI solutions stack and the RPC DRAM memory controller reference design will be available from Etron in Q3 2020.

>> This article was originally published on our sister site, Electronic Products.


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