Reflex CES , a provider of custom embedded and complex systems, has just released its Aurora-like IP Core based on Altera FPGAs. The new IP core is designed to allow interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs.
It features a fully compliant implementation of the Xilinx Aurora 8B/10B scalable, link-layer protocol for high-speed serial communication, and allows for communication between FPGAs through a backplane.
Based on the Xilinx Aurora 8B/10B, an open standard protocol used to transport data with higher connectivity performance for chip-to-chip and board-to-board architecture, the Aurora-like IP Core is designed to make it possible for to move data from point-to-point across one to sixteen serial lanes at 3.125 Gbps.
The core offers user flow control, native flow control, immediate and completion mode, and modules to convert interfaces to and from streaming Advanced eXtensible Interfaces (AXI).
This low protocol overhead IP core offers customers minimal data rate transfer latency with minimal logic resources – less than 900 equivalent logic cells for a 1 lane configuration- for cost effective implementation.
The Reflex CES Aurora-like 8B/10B IP Core is available now with VHDL source code, test-benches, a reference design and user guide. Reflex CES plans to ship an Aurora-like IP Core that supports communication between FPGAs with a 64B/66B protocol at 10 Gbps.