IEEE 1149.7 is a complementary superset of the widely adopted IEEE 1149.1 (JTAG) standard that has been in use for more than two decades. Although the new IEEE 1149.7 has not been finalized, its direction and its benefits to engineers–particularly those developing and debugging software for complex systems–are well defined.
IEEE 1149.7 was created with several goals in mind–to maintain backward compatibility with 1149.1 and improve debug performances. IEEE 1149.7 also reduces System-on-Chip (SoC) pin-count requirements and provides standardized power-saving operating conditions. While IEEE 1149.7 adds substantial functionality to the existing standard, it's important to note that IEEE 1149.7 isn't a replacement for IEEE 1149.1. Backward compatibility is maintained so that any board or system that integrates chips that support either standard is amenable to test or debug procedures.
The new standard offers designers several benefits, including:
• The ability to control debug-logic power consumption in an industry standard way. Whereas IEEE 1149.1 had a single “always on” state, IEEE 1149.7 offers four selectable power modes to enable ultra-low-power devices.
• The ability to quickly access a specific device in a system with multiple devices. By implementing a system level bypass, the scan chain is drastically shorter, which directly improves the debugging experience.
• The introduction of a star topology to complement the standard serial topology. Designers working with stacked-die devices, multi-chip modules and plug-in cards will favor the star topology because it simplifies the physical interdevice connections.
• Two-pin operation in addition to the four-pin operation required in IEEE 1149.1. Since most of today's systems integrate multiple ICs and have severe size constraints, reducing the number of pins and traces will help designers meet their form factor goals and allowing for additional functional pins and/or low package cost. Background Data transfers (BDX) provide an industry-standard method for sending instrumentation data. Instrumentation information was previously implemented in vendor-specific methods, making tools support difficult. Standardization will provide users with a greater selection of products.
Since much of the terminology and techniques used in the new standard are inherited from a present one, a brief review of IEEE 1149.1 will be useful.
In the mid-1980s, multilayer circuit boards and non-lead-frame ICs were becoming standard. But because the connections between ICs were not available to test probes in these subsystems, testing was becoming more and more difficult. The Joint Test Action Group (JTAG) was formed in 1985 to solve this problem.
Although considered synonymous with JTAG, the IEEE 1149.1 standard's official title is the Standard Test Access Port and Boundary-Scan Architecture. Among other things, it defines test access ports (TAPs) used for testing PC boards using boundary scan.
Today, JTAG is used not only for PC board testing but also to access sub-blocks of integrated circuits and to debug embedded systems.
The JTAG ecosystem begins with IC designers embedding test logic in each chip and connecting internal registers in the chip to JTAG scan chains. The hardware components of IEEE 1149.1 consist of:
• TAPs. Four mandatory pins are: TDI (test data in), TDO (test data out), TMS (test mode select), and TCK (test clock). An optional TRST/reset pin is also defined. When driven low, it resets the internal state machine.
• TAP controller: A finite state machine with 16 states with TMS and TCK as its inputs. Outputs include ClockDR, UpdateDR, shiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK, and the optional TRST.
• Instruction register.
• Test data register.
Figure 1 shows the basic IC architecture of IEEE 1149.1.
Test engineers use these structures as the access points for built-in self-test (BIST). Together, JTAG and BIST are widely used to deploy low overhead embedded test solutions that detect static faults such as shorts, opens, and logic errors.
For software debugging, design engineers use an in-circuit emulator to access an on-chip debug module, which is integrated into the CPU over the JTAG interface. This debug module provides software developers the ability to load, run, halt, and step the CPU.
Currently, the IEEE 1149.7 standard is headed for ratification in 2009. The IEEE working group that developed the new standard collaborated with and built upon the work of two other standards bodies: the Mobile Industry Processor Interface (MIPI) group and the NEXUS (IEEE ISTO 5001) Consortium.
The standard's capabilities are conveniently structured into six classes with each class building on the capabilities developed in the previous classes.
The first four classes (Class T0 though T3) are essentially extensions to IEEE 1149.1. The second group (Class T4 and T5) implements and uses advanced two-pin operation. By employing this step-wise development model, the working group made it easier to grasp the implications of the new standard and provide designers with the ability to implement the necessary capability for their devices.
Class T0 ensures compliance with the industry's current test infrastructure based on IEEE 1149.1. In class T0, after a test-logic-reset, all IEEE 1149.7 multi-tap devices must conform to the mandatory IEEE 1149.1 instruction behavior and implement a one-bit DR-scan for the bypass instruction.
Class T1 defines the control system upon which the advanced capabilities of the subsequent classes are based.
In brief, the innovative control system employs IEEE 1149.1-compatible TAP state sequences and shift-state watching to create a control system as the zero-bit DR Scans (ZBSs) are employed to set the state of an IEEE 1149.7-compliant chip while leaving IEEE 1149.1-compliant chips completely unaffected.
ZBS state sequences are rarely, if ever, used with the BYPASS and IDCODE instructions in IEEE 1149.1 systems and perform no real function (see Figure 2 ). This is because the ZBS with these instructions is benign and does not materially change the state of the test logic.
The yellow line in Figure 2 traces the path of a ZBS state sequence. The cartoon figure on the left of the diagram represents the control systems as it “watches” and counts the number of ZBSs the design engineer has initiated.
The ZBS begins at the Select-DR-Scan state through exit and proceeds to an Update-DR TAP controller state without changing anything in the TAP controller. As far as the IEEE 1149.1 standard is concerned, nothing of note has transpired.
However, logic represented by the cartoon face in Figure 2 keeps counting the number of times ZBS state sequences are initiated. When the ZBS sequence is broken by moving from the Capture-DR state to the Shift-DR state, the logic locks the ZBS count.
Locking the ZBS count activates a control level that is equal to the ZBS count (1 through 7). Control level two is used to create commands for the IEEE 1149.7 system. Control level functionality is shown in Table 1 .
A control level is exited when certain events occur. These events are the Select-IR-Scan controller state, the Test-Logic-Reset state, and certain controller commands and events that are meant to synchronize the operation of Class T4 and T5 controllers.
Class T1 is also helpful for controlling power. IEEE 1149.7 defines four power-down modes designed for use cases such as board testing, chip testing, and applications debugging. Defined power-down modes for the debug logic aids in reducing system power as well as provides a standard way for tools vendors to work with powered-down devices.
By implementing a chip-level bypass mechanism, Class T2 improves debugging performance for high chip-count applications by dramatically shortening the scan chain.
Since the TAP controllers in each chip are serially chained, prior to IEEE 1149.7, a design with many devices includes the TAP controller for each and every device in the scan chain. The example system in Figure 3 has three devices with five cores, contributing a total of 100 bits to the scan chain. If a developer wants to interrogate the last device on the chain he has to scan 100 bits each time. This can be quite inefficient, with the result that device access for embedded software developers is slower.
The new chip-level bypass capability in IEEE 1149.7 freezes the TAP controller inside the devices that are not of interest and reduces the number of scan bits from 100 to eight (Figure 3 ). This decreases the number of bits needed to be shifted out of the system, dramatically improving the performance of the scan chain.
This mechanism can also function as a firewall. A firewall is useful for hot-connections to a target board while it's in operation. In IEEE 1149.1 systems, connecting to a running target may result in unpredictable operation, possibly caused by electrical issues resulting from the connection that may confuse the debug logic. With the bypass mechanism operating as a firewall, access to chip TAP is possible only after a predetermined sequence is initiated. This step ensures that a debug test system will connect only after a target has a stable electrical connection.
Through the use of chip-select mechanisms and link-ID assignments, Class T3 allows developers to create star configuration instead of the traditional serial configuration of the IEEE 1149.1 standard. T3 implements a Star-4 or Wide Star as illustrated in Figure 4 .
In order to create a star configuration, the chips involved must be numbered. On start up, however, they do not have a number registered with the controller. Class T3 defines a method in which they are assigned numbers, essentially though a process of elimination based on their IDCODE and unique ID.
Class T3 creates a star configuration that enables the significant innovation of two-pin operation, which is implemented in Class T4. It should also be noted that upon power-up an IEEE 1149.7 system is compatible with IEEE 1149.1. By configuring the IEEE 1149.7 logic through ZBS, the advanced capabilities of IEEE 1149.7 become available.
Whereas Classes T0 through T3 can be seen as extensions to the IEEE 1149.1 standard, Class T4 provides a quantum leap in functional value. The main benefit is the reduction in required pins from four to two, and the introduction of new scan formats that support optimized transactions, which maintain and improve performance in the reduced pin configuration.
When device die are stacked, it is better to have the fewest number of connectors possible because this increases the difficulty to stack the die. The fewer number of connectors, the easier the task since each connector adds additional costs.
In brief, the key to the two-pin operation is the elimination of the original data lines (TDI/TDO) and the bi-directional transmission of serialized data over the TMSC line.
Reducing pin count with glue-less star configurations is a valuable feature for system designers who use the stacked die and multichip modules because it simplifies the arrangement of debug pins on the mounting points and this, in turn, makes manufacturing, mounting, and stocking of parts easier and thus less expensive.
To implement this capability, the glue-less star configuration from Class T3 is used, this time without TDI and TDO. This process is illustrated in Figure 5 inthe Star-2 or narrow-star configuration.
In addition to reducing pin count, Class T4 defines optimized download-specific scan modes. In these modes, only useful information is downloaded. To improve performance of reduced-pin operation, the clock rate can be doubled. This, along with the optimized transactions just described, means performance is maintained and, in some use cases, improved.
Class T5 gives the test port the ability to concurrently perform debug and instrumentation operations, which reduces the number of pins dedicated to instrumentation. This reduction is possible because instrumentation data is transferred during idle time, which is quite ample for the task. Typically two pins are dedicated for instrumentation.
Class T5 also allows for custom protocols. This feature is incorporated in the standard in large part because the working group recognized that many device vendors already had custom protocols. Class T5 standardizes the process to enable the use of custom protocols while ensuring an industry standard method of enabling them is implemented.
Chip designers wishing to implement IEEE 1149.7 functionality in their devices can include a protocol converter on the device. The converter makes it simple to add basic IEEE 1149.7, such as reduced pin connectivity to existing IP that may only be compatible with IEEE 1149.1. For example, Figure 6 illustrates a sample two-core device with IEEE 1149.1 support. If chip designers want to add IEEE 1149.7 support, they simply include a protocol converter on the device. The benefit of doing this would be that the debug logic of Core A and Core B would not need to change. Also, since the IEEE 1149.7 system can also transport instrumentation data in the background, two more pins are reduced from the system, resulting in a device requiring only two functional pins, as shown in Figure 7 .
From Figure 7 , it's also possible to use a protocol converter to allow existing IEEE 1149.1 systems to work with IEEE 1149.7 devices. This enables re-use of existing software and hardware infrastructure and lowers the entry cost for end users.
Two pins better than four
IEEE 1149.7 was created with several goals in mind–specifically to maintain backward compatibility with IEEE 1149.1 and improve debug performances. IEEE 1149.7 also reduces System-on-Chip (SoC) pin-count requirements and provides standardized power-saving operating conditions. The new standard also aims to simplify manufacturing of multichip modules and stacked-die devices and accommodates existing practices that deviate from the IEEE 1149.1 standard.
Stephen Lau is the product manager for emulation technology at Texas Instruments. His responsibilities include marketing, product definition (end-user product and IP), and managing strategic third-party partnerships and customers. You may reach Stephen Lau at .