Reliable systems for micro aerial vehicles - SoC evaluation -

Reliable systems for micro aerial vehicles — SoC evaluation


Editor's Note: Embedded designers must contend with a host of challenges in creating systems for harsh environments. Harsh environments present unique characteristics not only in terms of temperature extremes but also in areas including availability, security, very limited power budget, and more. In Rugged Embedded Systems, the authors present a series of papers by experts in each of the areas that can present unusually demanding requirements. A separate excerpt of the book addresses fundamental concerns in reliability and system resiliency.

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Adapted from Rugged Embedded Systems, Computing in Harsh Environments, by Augusto Vega. Pradip Bose, Alper Buyuktosunoglu.

CHAPTER 7. Reliable electrical systems for micro aerial vehicles and insect-scale robots: Challenges and progress (Cont.)
By X. Zhang, Washington University, St. Louis, MO, United States


To demonstrate improved resilience and performance of our proposed adaptive clocking across a wide range of supply voltage, measurement results were obtained from the prototype SoC chip (Fig. 12) fabricated in TSMC’s 40 nm CMOS technology. We use the maximum error-free operating frequency of the memory performing BIST as a proxy metric, because it is often the on-chip SRAM sharing the same voltage domain with the digital logic that limits the system performance at lower supply levels. Also, the retention voltage of the SRAM cells typically determines the minimum operating voltage of the system [21].

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FIG. 12 Die photo of the fully integrated prototype system-on-chip.

First, we characterize the voltage versus frequency relationship of the SRAMs using external sources in order to determine the efficacy of using the DCO for adaptive-frequency clocking. Then, we compare the fixed- and variable-frequency clocking schemes with a regulated voltage generated by the SC-IVR in closed-loop operation. Lastly, we present the advantages of combining adaptive clocking with a variable voltage provided by operating the SC-IVR in open loop.

5.4.1 Frequency versus voltage characterization

The on-chip SRAMs were characterized at static supply voltage levels provided externally via EXTVDD, in order to determine the SRAM’s voltage to frequency relationship under quiet supply conditions. Using an external clock (EXTCLK) at different fixed frequencies, we obtained the Shmoo plot in Fig. 13A. It shows (1) the minimum retention voltage of SRAM cell is between 0.6 and 0.65 V; (2) the maximum SRAM frequency scales roughly linear with supply voltage and ranges from 68 at 0.65 to 256 MHz at 1.0 V; and (3) the maximum SRAM frequency closely correlates with DCO frequency plot for control code D1⁄410. This correlation suggests the FO4-delay-based DCO tracks the critical path delay in the SRAM across a wide supply range and should enable error-free memory BIST for control word D above 10. We experimentally verified this by turning on the internal DCO to provide the system clock instead of using EXCLK and sweeping the same voltage range via EXTVDD. The resulting Shmoo plot in Fig. 13B further demonstrates the DCO’s ability to track SRAM delay at different static supply voltage levels. Considering process and temperature variations, the same control word D1⁄410 may not apply to chips from all process corners and over all temperature ranges. However, since the process and temperature conditions are relatively static, and our results show that a fixed control word can cover the range of fast-changing supply variation, it is possible to determine this fixed control word during the calibration phase before the normal operation of the robotic system starts.

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FIG. 13 Shmoo plots for two different clocking schemes. (A) External clock at fixed frequencies and (B) internal adaptive clock generated by the DCO at different control code D.

5.4.2 Fixed versus adaptive clocking with regulated voltage

Having verified the DCO, we now compare fixed- and adaptive-frequency clocking schemes for a system that operates off a regulated voltage with the SC-IVR operating in closed loop. We also emulate noisy operating conditions using the on-chip ILOAD generator that switches between 0 and 15 mA at 1 MHz. Measurements made via the on-die voltage monitoring circuit showed approximately `70 mV worst-case ripple about a mean voltage of 0.714 V.

For the conventional fixed-frequency clocking scheme, the maximum operating frequency ought to depend on the worst- case voltage droop, measured to be 0.647 V. Using the measured relationship in Fig. 13A, the maximum frequency cannot exceed 68 MHz. To measure the actual maximum error-free frequency, we performed 100 independent BIST runs using the EXTCLK, set to a fixed frequency and recorded the failure rate. Fig. 14A summarizes the measured failure rates across different externally driven operating frequencies. These results show that the maximum error-free frequency is below 55 MHz for the fixed-frequency clocking scheme, which is even lower than the anticipated 68 MHz, perhaps attributable to the additional noise injection.

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FIG. 14 Comparison of memory BIST failure rates for fixed- versus adaptive- frequency clocks, but under the same IVR closed-loop regulation. (A) Fixed-frequency externally and (B) adaptive-frequency from DCO.

Using the same IVR configuration and test conditions, Fig. 14B plots the failure rates versus different digital control codes of the DCO. At D =10, there were intermittent failures, attributable to the additional noise not present in the prior experimental results of Fig. 13B. The adaptive-frequency clocking scheme delivers consistent and reliable operation at D1⁄411. Based on the average DCO frequency measured during the tests and also plotted in Fig. 14B, corresponds to an average frequency of 111 MHz, which is 2 the fixed-frequency clocking scenario. Here we use the average frequency instead of the worst frequency as a measure of system performance, because the operating frequency, which tracks the noisy supply, changes at much faster time scale than the task performance requirement of the robot, which means that the aggregated throughput measured by the average frequency is the more meaningful metric and occasional drop to lower frequency does not have destructive effect on the system.

We attribute this large frequency difference between the two clocking scenarios to a couple of factors. Fixed-frequency clocking requires sufficiently large guardbands to guarantee operation under the worst-possible voltage droop condition. In contrast, adaptive-frequency clocking allows both the clock period and load circuit delays to fluctuate together as long as both vary with voltage in a similar manner. Hence, the guardband must only cover voltage-tracking deviations between the DCO and load circuit delay paths across the operating voltage range of interest, and can be built into the DCO. Another factor that penalizes the performance of the fixed-frequency clocking comes from the additional noise on the EXTCLK signal for crossing the TVDD to DVDD boundary.

This series on the RoboBee MAV concludes in the next article with a further discussion of the impact of the adaptive-frequency clocking technique.  

Reprinted with permission from Elsevier/Morgan Kaufmann, Copyright © 2016

Professor Zhang joined the faculty at Washington University in St. Louis in 2015. Previously, she was a postdoctoral fellow in computer science at Harvard University, where she worked on the RoboBee BrainSoC and energy-efficient computing projects. She has worked as a graduate research assistant at Cornell University studying variability-tolerant circuits. Zhang earned a doctorate in electrical and computer engineering at Cornell University in 2012. She earned a bachelor’s degree in electrical engineering at Tsinghua University in Beijing in 2006.

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