Editor's Note: Embedded designers must contend with a host of challenges in creating systems for harsh environments. Harsh environments present unique characteristics not only in terms of temperature extremes but also in areas including availability, security, very limited power budget, and more. In Rugged Embedded Systems, the authors present a series of papers by experts in each of the areas that can present unusually demanding requirements. A separate excerpt of the book addresses fundamental concerns in reliability and system resiliency.
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Adapted from Rugged Embedded Systems, Computing in Harsh Environments, by Augusto Vega. Pradip Bose, Alper Buyuktosunoglu.
CHAPTER 7. Reliable electrical systems for micro aerial vehicles and insect-scale robots: Challenges and progress (Cont.)
By X. Zhang, Washington University, St. Louis, MO, United States
5.3 SYSTEM IMPLEMENTATION
The prototype microrobotic SoC designed as the precursor of BrainSoC is not a full-fledged implementation of all the functionalities for the RoboBee, but it captures the most essential components in such a SoC for our investigation of the interaction between supply noise and clocking scheme. Shown in Fig. 8, the prototype SoC contains a fully integrated two-stage 4:1 SC-IVR, a 32-bit ARM Cortex-M0 general-purpose processor, two identical 64 KB memories, and a programmable DCO that generates the voltage-tracking adaptive-frequency clock. To gather measurement data for performance evaluation, the chip also includes numerous blocks for testing and debug purposes: a built-in self-test (BIST) block allows thorough testing of the two memory blocks; a scan chain configures the digital blocks; a voltage monitor block probes internal voltages to record fast transients on the supply line; and a current-load generator enables different testing scenarios for load current-induced supply-noise. Lastly, the prototype chip provides direct interfaces for external power and clock sources to set up different operating modes.
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FIG. 8 Block diagram of the fully integrated prototype system-on-chip.
5.3.1 Switched-capacitor integrated voltage regulator
The SC-IVR converts the battery voltage (VBAT =3.7 V) down to the digital supply (DVDD =0.7 V). It consists of a cascade of two 2:1 switched-capacitor converters that are respectively optimized for high input voltage tolerance and fast load response and individually tuned to maximize conversion efficiency, and each converter stage employs a 16-phase topology to reduce voltage ripple. A low-boundary feedback control loop can regulate DVDD to a desired voltage level. A thorough discussion of the SC-IVR and its implementation details can be found in .
While this SC-IVR can achieve high conversion efficiency, 70% at its optimal operating point, it is subject to the inherent limitations of any switched-capacitor based DC-DC converter; efficiency varies with respect to input and output voltages and the load current level. As an example, Fig. 9 plots the SC-IVR’s output voltages at different battery voltage levels for both open- and closed-loop operation, and the peak efficiency is labeled at each point. These efficiency numbers and output voltage levels are derived by sweeping the output voltage to find the peak conversion efficiency and its corresponding output voltage level at each fixed input battery voltage, and hence each point presents the best possible efficiency for each input and output voltage combinations. The data in Fig. 9 clearly shows that open-loop operation consistently offers 2–3% higher conversion efficiency and 16–30 mV higher output voltage levels than closed-loop operation, resulting in both higher efficiency and higher performance for the SoC.
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FIG. 9 Output voltages at peak conversion efficiency versus battery voltage for open- and closed-loop operation.
Fig. 10 plots the transient behavior of the IVR with respect to load current steps between 3 and 50 mA for both open- and closed-loop operation. According to the transient waveform of the output voltage, the closed-loop operation quickly responds to avoid the steep voltage droop otherwise seen in the open-loop case; however, it exhibits larger steady-state voltage ripple, especially for higher load currents, due to the control loop implementation and feedback delay.
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FIG. 10 Transient response of SC-IVR output voltage to load current steps.
The voltage ripple in closed-loop operation is caused by the delay of the feedback control that prevents the regulator from instantaneous reaction when its output voltage drops below the reference voltage and thus can result in both undershoot and overshoot in the output voltage. Even with sophisticated feedback strategy and fast transistors in advanced technology node, it is difficult to reduce the feedback delay beyond 1 ns, and this fundamentally determines the magnitude of the steady-state closed-loop ripple. On the other hand, the voltage ripple in open-loop operation is due to charge sharing between the flying capacitor and the decoupling capacitor at the output node. It can be reduced by phase interleaving, and therefore does not experience the same fundamental limit as the closed-loop ripple. This is why in our 16-phase interleaved implementation of the IVR, the open-loop ripple magnitude is significantly smaller than the closed-loop ripple.
5.3.2 Digitally controlled oscillator
Our proposed adaptive-frequency clocking scheme needs a clock generator whose frequency tracks closely with changes in supply voltage. This allows the operating frequency of the digital load circuitry to appropriately scale with voltage fluctuations, providing intrinsic resilience to supply noise. There are numerous examples of critical-path-tracking circuits for local timing generation [14,20]. Instead, we use a programmable DCO to generate the system clock. The DCO contains a ring of programmable delay cells comprising of transmission and NAND gates that approximate a typical fanout-of-4 inverter delay.
As shown in Fig. 11A, a 7-bit digital code, D=D6 ,…,D1 D0 , sets the DCO frequency by selecting the number of delay cells in the oscillator loop. While our implementation uses 7 bits of control code, measurement results show that the lower 4 bits are sufficient for the normal operating range of the digital system. Fig. 11B plots DCO frequency versus supply voltage (DVDD) across a range of the digital control codes. Over the measured voltage range (0.6–1 V), frequency scales roughly linearly with supply voltage, but slightly flattens out for voltages below 750 mV. The uneven frequency spacing with respect to the control code D results from the delay cell’s asymmetric design and should be improved for future implementation.
5.3.3 Cortex-M0 and memory
Both the Cortex-M0 microprocessor and the memories used in the prototype SoC are IP blocks provided by our collaborators. To facilitate our testing strategy for different operation modes, the Cortex-M0 and one of the 64 KB memories (SRAM1) are intentionally designed to share the voltage domain (DVDD) with the DCO, while the other memory (SRAM0) sits in another separate voltage domain (TVDD) with the rest of the test peripheral circuits. Except for being in a different voltage domain, SRAM0 shares the same physical design as SRAM1 as both are using the same hard memory IP.
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FIG. 11 Digitally controlled oscillator (DCO) schematic and measured characteristics. (A) DCO schematic and (B) DCO frequency versus DVDD at digital control code D.
5.3.4 Built-in self-test module
A BIST module performs at-speed test for both SRAMs. To make sure full test coverage of all the memory cells, the BIST performs a modified MARCH-C routine that writes to and reads different data patterns from each memory address in the SRAMs successively. At the conclusion of the MARCH-C routine, the BIST module would raise a pass/fail flag if any read or write error has been detected. Due to the limited storage for testing vectors, only the address and data of the last failure are recorded for posttest analysis.
The test peripheral circuits operated off a TVDD include a voltage monitor block that captures fast nanosecond-scale transient changes of the supply line and a programmable load current generator that is made up of differently weighted switched current sources. Although external supply and clock interfaces such as TVDD, EXTVDD, and EXTCLK are included, they are for testing purposes only, as the SoC is capable of operating directly off the battery without any external supply or clock reference.
This series on the RoboBee MAV continues in the next article with a discussion of experimentation evaluation of the prototype SoC.
Reprinted with permission from Elsevier/Morgan Kaufmann, Copyright © 2016
Professor Zhang joined the faculty at Washington University in St. Louis in 2015. Previously, she was a postdoctoral fellow in computer science at Harvard University, where she worked on the RoboBee BrainSoC and energy-efficient computing projects. She has worked as a graduate research assistant at Cornell University studying variability-tolerant circuits. Zhang earned a doctorate in electrical and computer engineering at Cornell University in 2012. She earned a bachelor’s degree in electrical engineering at Tsinghua University in Beijing in 2006.