This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.
Clock generators that employ PLLs are widely used in network equipment for generating high-precision and low-jitter reference clocks, or for maintaining a synchronized network operation.
Most clock oscillators give their jitter or phase noise specification using an ideal, clean power supply. In a practical system environment, the power supply can suffer from interference due to on-board switching supplies or noisy digital ASICs.
To achieve the best performance in a system design, it is important to understand the effects of such interference. First, we examine the basic power supply noise rejection (PSNR) characteristics of a PLL-based clock generator. Following that, we look at how to extract timing jitter information from measurements taken in the frequency domain.
These techniques are then applied, and several different measurement methodologies are compared using lab bench testing. Finally, we summarize the merits of the preferred approach.
A typical PLL clock generator is shown Figure 1 below . Since the output driver can have very different PSNR performance for different types of logic interfaces, the following analysis will focus on the supply noise impact to the PLL itself.
|Figure 1: Shown is a typical topology for a PLL clock generator.|
Figure 2 below shows the PLL phase model assuming that the power supply noise VN is injected into the PLL/VCO, and the divide ratios, M and N are set to 1.
|Figure 2: Shown is the PLL phase model assuming that the power supply noise V N is injected into the PLL/VCO, and the divide ratios, M and N are set to 1|
The PLL closed loop transfer function from VN(s) to Φo (s) is given by:
For a typical second order PLL:
Here ω3dB is the PLL 3dB bandwidth, ωz is the PLL zero frequency, and ωz << ω3dB .
The equations above demonstrate that in a PLL clock generator, the power supply noise is rejected by 20dB/dec when the supply interference frequency is greater than the PLL 3dB bandwidth.
For power supply interference frequencies between ωz and ω3dB , the output clock phase varies with the power supply interference amplitude as:
As an example, Figure 3 below shows the PSNR characteristics of a PLL for two different settings of the PLL's 3dB bandwidth.
|Figure 3: Here are the typical PLL power-supply noise rejection characteristics.|
Conversion of power spectrum spurs to DJ
When a single tone sinusoidal signal, fm , is applied to the power supply of a PLL, it produces a narrow- band phase modulation at the clock output, which can be generally described using Fourier series representation:
Here β is the modulation index representing the maximum phase deviation. For a small index modulation (β<<1), the Bessel function can be approximated as:
Here n = 0 represents the carrier itself. When n = 1, the phase modulated signal is given by:
The equation below demonstrates that, when measuring the double sideband power spectrum Sv (f), if variable x represents the level difference between the carrier at fo and the fundamental sideband tone at fm , then:
deviation in radians, the peak-to-peak deterministic jitter caused by this small index phase modulation can be derived as:
This analysis assumes that there is no amplitude modulation contributing to the tone at fm . In reality, both amplitude and phase modulation can be generated, reducing the accuracy of this approach.
Phase noise spectrum
To avoid the amplitude modulation effect when measuring the power spectrum SV (f), one can instead calculate the DJ by measuring the spur in the phase noise spectrum while applying a single tone sinusoidal interference on the supply.
With the variable y (dBc) representing the measured single-sideband-phase spurious power at frequency offset fm , the resultant phase deviation ΔΦ (radrms ) can be derived as:
It should be noted that the single-sideband phase spectrum in this analysis is not the folded version of the double-sideband spectrum. That is the reason for the 3dB component in the previous equations.
|Figure 4: Shown is deterministic jitter vs. phase spurious power.|
Figure 4 above shows the relationship between the deterministic jitter and the phase spurious power given by the previous equations.
PSNR measurement techniques
Following are five different ways of measuring the PSNR of a clock source, using the MAX3624 low-jitter clock generator as an example.
The measurement setup shown in Figure 5 below uses a function generator to inject a sinusoidal signal onto the power supply of the MAX3624 evaluation board.
|Figure 5: Shown is a PSNR measurement setup.|
The amplitude of the single-tone interference is measured directly at the VCC pin close to the IC. A limiting amplifier, MAX3272, is used to remove amplitude modulation, followed by a balun that converts the differential output into a single-ended signal for driving the different test equipment.
To compare the results from different tests, all the measurements were done under the following conditions:
Clock output frequency: fo = 125MHz
Sinusoidal modulation frequency: fm = 100kHz
Sinusoidal signal amplitude: 80mVP-P
Method 1: Power spectrum measurement. When observed on a power spectrum analyzer, the narrow-band phase modulation appears as two sidebands around the carrier.
Figure 6 below shows the case when viewed using the spectrum monitor function of the Agilent E5052.
The measured first sideband amplitude relative to carrier amplitude is -53.1dBc, which translates to 11.2psp-p deterministic jitter according to the earlier equations.
|Figure 6: Shown is the case when viewed using the spectrum monitor function of the Agilent E5052.|
Method 2: SSB phase spurious measurement. On a phase noise analyzer, the power supply interference will manifest itself as a phase spur relative to the carrier. The measured phase noise spectrum is plotted in Figure 7 below . The phase spurious power at 100kHz is -53.9dBc, which translates to 10.2 psp-p deterministic jitter using the earlier equations..
|Figure 7: Here is a plot of the measured phase noise spectrum.|
Method 3: Phase demodulation measurement . Using the Agilent E5052 signal analyzer, the phase-demodulated sinusoidal signal at 100kHz is measured directly (Figure 8 below ), which gives the maximum phase deviation from its ideal position. The peak-to-peak phase deviation is 0.47deg, which translates to 10.5 psp-p at an output frequency of 125MHz.
|Figure 8: Using the Agilent E5052 signal analyzer, the phase-demodulated sinusoidal signal at 100kHz is measured directly, which gives the maximum phase deviation from its ideal position.|
Method 4: Real time scope measurement. In a time domain measurement, the deterministic jitter caused by power-supply interference can be obtained by measuring the time interval error (TIE) histogram.
On a real-time scope, the clock output TIE distribution will appear as a sinusoidal probability density function (p.d.f) when a single-tone interference is injected into the PLL. The deterministic jitter can be estimated using the dual-Dirac model by measuring the peak distance between the mean of two Gaussian distributions from the TIE histogram.
Figure 9 below shows the measured TIE histogram using the Agilent Infiniium DSO81304A 40GSa/s real-time scope. The measured peak separation is 9.4ps under the test condition mentioned above.
|Figure 9: Shown is the measured time-interval error histogram.|
It should be noted that the memory depth of the real-time scope may limit the low sinusoidal modulation frequency that can be applied to the PLL supply.
For example, if the test equipment has a memory depth of 2MSps when the sample rate is set to 40GSps, that would only allow capture of jitter frequency components down to 20kHz.
Method 5: Sampling scope measurement . When a sampling scope is used, a synchronous trigger signal is required for analyzing the clock jitter under test. Two triggering methods can be used for TIE measurements.
The first solution is to apply a low jitter reference clock to the input of the PLL clock generator and use the same clock source as the trigger for the sampling scope. Figure 10a below shows the measured TIE histogram, which gives a peak spacing of 9.2ps.
|Figure 10: Time-interval error histograms are shown for various trigger conditions triggered by REF_IN (a), Self-triggered, T = 5 microseconds (b), and for Peak Spacing vs. Time Delay from Trigger (c).|
The advantage of triggering with a reference clock is that the measured TIE histogram peak separation is independent of the horizontal time delay from the trigger position. However, the measured TIE histogram might be affected by the triggering clock jitter. Therefore, it is important to use a clock source that has much lower jitter than the clock generator device under test.
The alternate approach that eliminates the impact of triggering clock jitter uses self triggering. In this case, the output of the clock generator under test is separated into two identical signals using a power splitter.
One signal is applied to the data input of the sampling scope, another one to the trigger input. Since the triggering signal contains the same deterministic jitter as the test signal, the histogram peak separation varies when the horizontal position of the scope main time base is swept through one period of the sinusoidal modulation frequency.
At a horizontal position of half period of the modulation signal, the peak separation on the TIE histogram will be twice the deterministic jitter from the test signal.
Figure 10b above shows the measured MAX3624 TIE histogram when the horizontal time delay is set to 5?s. The estimated TIE peak separation is 19ps, which gives an equivalent deterministic jitter of 9.5psp-p .
Figure 10c above shows the measured TIE histogram peak spacing at different horizontal time delay from the trigger point. For comparison, the TIE result is also shown when the sampling scope is triggered by a reference clock input.
Table 1 below summarizes the measured deterministic jitter at the MAX3624 125MHz clock output, using the different methods discussed.
|Table 1: Here is a summary of the measured deterministic jitter at the MAX3624 125MHz clock output using the different methods.|
It should be noted that measured DJ using a dual-Dirac approximation from the TIE histogram is slightly smaller than the DJ obtained from the frequency-domain spectral analysis.
This is caused by the process of convolution of the SJ p.d.f. with the Gaussian distribution of the random jitter components.
Thus, DJ extracted from the dual-Dirac model is only an estimation and should only be applied when the standard deviation of the random jitter is much smaller than the distance between the two peak separations of the jitter histogram.
For the relatively large interference used in the examples, the results were well correlated. However, when the level of interference drops relative to the random jitter, the time domain methods become less accurate.
Furthermore, if the clock signal is corrupted by amplitude modulation, measurements using a power spectrum analyzer become unreliable.
Therefore, of all the methods presented, the phase spur power measurement using a phase noise analyzer is the most accurate and convenient way to characterize the PSNR of a clock generator.
The same method can be extended for evaluating the deterministic jitter aspect caused by other spurious products appearing on the phase noise spectrum.
Sharon Wang is Senior Corporate Applications Engineer and John Abcarius is a senior member of the technical staff at Maxim Integrated Products Inc.