Renesas expands options with Andes-based RISC-V MPU -

Renesas expands options with Andes-based RISC-V MPU

RZ/Five general-purpose MPUs allow developers to choose from RISC-V and Arm based core options.

Renesas Electronics Corporation said it has expanded the options for developers using its general-purpose microprocessor units (MPUs), with a new MPU built around a 64-bit RISC-V CPU core from Andes Technology.

Its new RZ/Five general-purpose MPUs employs the Andes AX45MP, based on the RISC-V CPU instruction set architecture (ISA). The RZ-Five augments Renesas’ previously available Arm CPU core–based MPUs, providing customers with more options and flexibility in the product development process.

The new RZ/Five is optimized to provide the performance and peripheral functions required in IoT endpoint devices, such as gateways for solar inverters or home security systems, to collect sensor data and connect to servers or to the cloud. Its maximum operating frequency is 1 GHz. Peripheral functions include support for multiple interfaces, such as two Gigabit Ethernet channels, two USB 2.0 channels, and two CAN channels, as well as dual A/D converter modules. Support is also provided for connecting external DDR memory with error checking and correction (ECC) and security functions.

Renesas RZFive_lineup
Renesas general purpose MPU lineup provides both RISC-V and Arm Cortex based options for developers. (Source: Renesas Electronics)

As with the RZ/G Series, which are based on the Arm Cortex processors, a verified Linux package (VLP) featuring Civil Infrastructure Platform (CIP) Linux, an industrial-grade Linux offering long-term maintenance support for more than 10 years, is available for RZ/Five. This makes the RZ/Five series suitable for corporate infrastructure and industrial applications that require reliability and extended service life. It also allows users to reduce future Linux maintenance costs.

The peripheral functions and package for the RZ/Five are compatible with those of the Arm core–based RZ/G2UL, allowing for reuse of existing proven designs. The smaller RZ/Five package makes it suitable for less complex designs more efficiently. An RZ SMARC evaluation board kit will be offered with a module board conforming to the SMARC 2.1 standard, equivalent to the currently available environment for the RZ/G Series. This allows switching and evaluating between an RZ/Five CPU module and an RZ/G2UL CPU module, enabling easier evaluation and contributing to the shortening of product development cycles.

Commenting on the release of the new MPU, Renesas’ senior vice president and head of SoC in its IoT and infrastructure business unit, Hiroto Nitta, said, “I am delighted that Renesas is among the first to announce a general-purpose MPU built around a 64-bit RISC-V CPU core from Andes. With the introduction of the RZ/Five MPUs along with ecosystem support, Renesas is taking the lead in providing RISC-V solutions ahead of the market.”

Andes Technology’s chairman and CEO, Frankwell Lin, said, “Andes has collaborated with Renesas first on the 32-bit RISC-V core and now on the 64-bit AX45MP, and I anticipate that this development will lead to the early adoption of customers’ devices in the global market built with Andes’ advanced RISC-V processor families.”

Renesas will provide a complete system solution for the RZ/Five CPU module including Renesas’ DA9062 power management IC, 5P35023 programmable clock generator, AT25QL128A flash memory and SLG46538 GreenPAK IC implementing peripheral functions such as system reset. Samples of the RZ/Five MPUs are available now, and mass production is scheduled to begin in July 2022.

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