RISC core design software in free trial - Embedded.com

RISC core design software in free trial


Cambridge, UK — Cambridge Consultants has released a web-downloadable toolkit for its royalty-free RISC processor core, XAP2. The free-trial software development kit allows users to write and simulate application software in C or assembler, to evaluate the 16-bit processor's architecture for use in an SoC ASIC or FPGA project.

The CCL XAP2 RISC core and toolkit provides technology that can be implemented in as few as 12,000 gates. It is available as synthesisable RTL for use in FPGAs or with any ASIC silicon foundry offering a gate library. Its licence that requires no royalties per chip.

The XAP2 SDK runs under Windows on a PC. It includes a software development toolchain that will take a program written in C or assembler, compile and link the code, and execute it on a simulator. When users decide to take a XAP2 licence, they have access to a complete integrated development environment with rich debugging facilities. This includes an FPGA-based hardware emulation tool, and in-system fault analysis based on CCL's patented non-invasive real-time SIF serial debugging interface. This accesses all of XAP2 address space while the core is running, without inserting any time delays.

CCL also offers a XAP2 hardware emulator card. The XAP2 core complete with 8kB of RAM can be contained in less than 20% of the Xilinx XC2V3000 FPGA used in the emulator, leaving space for custom digital circuitry required for the rest of the product. It also has a defined connector interface for analogue daughter cards, so that a complete SoC can be emulated in hardware. CCL claims that FPGA implementations have been tested at 16MHz and faster speeds have been achieved in ASIC silicon.

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