RISC-V based CPU supports automotive functional safety - Embedded.com

RISC-V based CPU supports automotive functional safety

The new NS31A from NSITEXE is a new RISC-V based 32-bit general purpose CPU that supports ISO 26262 ASIL D level functional safety for automotive applications.

A new RISC-V based 32-bit general purpose CPU that supports ISO 26262 ASIL D level functional safety for automotive applications has been introduced by Japan-based intellectual property (IP) vendor NSITEXE, a spinout of Denso Corporation.

The NS31A is a general-purpose CPU for controlling various embedded systems including automotive applications. It features a single-issue, in-order four-stage pipeline using the 32bit RISC-V instruction set architecture (RV32IMAF). It supports ISO 26262 ASIL D functional safety required for automotive applications, and also supports a privileged mode as required for the AUTOSAR platform.

NSITEXE NS31A architecture
The NS31A is a general-purpose CPU with a single-issue, in-order 4-stage pipeline that uses a 32bit RISC-V ISA (RV32IMAF). (Source: NSITEXE)

The CPU is based on NSITEXE’s DR1000C data flow processor which recently achieved ISO 26262 ASIL D ready certification from SGS-TÜV. The DR1000C is a parallel processor IP that is ideal for offloading high-load arithmetic processing (like model predictive control, artificial intelligence (AI) inference, and sensor processing) required by automotive microcontrollers targeted at safety critical systems. Up to 16 hardware threads efficiently utilize a vector processor, thereby achieving extremely high-power performance, according to the company. The DR1000C is suitable for vehicle control as well as for various embedded applications such as industrial equipment in factory automation and radar and other sensor processing.

The DR1000C has integrated hardware safety features including error correction code (ECC) for memories, dual-core lockstep architecture, bus protocol violations detection, and an error management unit that injects errors for self-diagnosis, reports errors to the host system, and manages their statuses. These features enable this processor to meet ASIL D safety requirements without the need to add any external special safety mechanism.

NSITEXE DR1000C block diagram
The DR1000C is a parallel processor IP that is ideal for offloading high-load arithmetic processing (like model predictive control, artificial intelligence (AI) inference, and sensor processing) required by automotive microcontrollers targeted at safety critical systems. (Source: NSITEXE)

Two safety mechanisms (hardware checker and software test) are available for the main part of DR1000C vector processing unit. Users can choose these mechanisms according to the performance requirements of the application as well as the target ASIL. The hardware checker with its lockstep architecture enables ASIL D random hardware fault detection requirements to be met. In addition, ASIL C requirements will be met by upcoming software test libraries, enabling the computational power of the vector processing unit to be fully exploited.

The ASIL D-compliant DR1000C-SDK (software development kit) provides secure and accurate thread control as well as memory protection and temporal protection features. By utilizing these features and the ISO 26262-compliant tool chain, the user can focus on application development, potentially leading to a shorter development time. The thread control software included in the SDK has a variety of features necessary for a safety critical system, such as priority execution of real-time tasks and thread execution monitoring.

The NS31A-HSK (hardware safety kit) provides failure modes effects and diagnostics analysis (FMEDA), a safety manual, safety case reports, and ISO 26262-related documentation. It reduces the amount of time required to analyze the functional safety of an automotive microcontroller as well as to achieve its certification.

Embedded Workbench development toolchain

Open-source software (OSS) based development tools are available on the NS31A. For functional safety development, IAR Systems’ Embedded Workbench for RISC-V, available with certification according to ISO 26262 and other standards, will support the CPU as a standard feature. This is provided as a result of a partnership between NSITEXE and IAR Systems, and available to customers through EDA tools and semiconductor IP distributor NeXtream Corporation.

Stefan Skarin, CEO of IAR Systems, said, ““Our collaboration with NSITEXE brings our joint strong technology and services further into the RISC-V community with extended possibilities for functional safety development. IAR Systems’ functional safety offering provides the widest standards coverage in the industry, and together with NSITEXE, we are now enabling companies to speed up the path of using RISC-V in applications where ensured safety is critical for success.”

Hideki Sugimoto, CTO, NSITEXE, added, “Our development efforts have been focused on three pillars – versatility, efficiency, and functional safety – with massive future trends in mind. The NS31A implements these as a RISC-V 32-bit general-purpose CPU with high functional safety for users who want to control embedded systems easily, reasonably, and safely. The NS31A offers reliability not just for automotive applications but also for many embedded systems that require high levels of safety in fields such as factory automation and medical care.”

“Building on this effort for high functional safety as well as on our innovative processor technology, we support smart mobility and MaaS [mobility-as-a-service], thus contributing to changing the world in ways that enrich people’s lives,” said Sugimoto.

NSITEXE is an IP vendor established in 2017 as a spinout of Denso Corporation, specializing in the development of advanced processors. The company develops RISC-V based processor IPs that support functional safety.


Related Contents:

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.