RISC-V ready to come of age

Zurich – Over the last year or so, we’ve heard many times that ‘this is the moment for RISC-V’. So, this week, I attended the RISC-V workshop in Zurich to get an idea of where it really is at right now. The conclusion: while there is still a lot of background work to be done for RISC-V to go mainstream, the signs are that all the triggers to make it happen are now gradually being released.

The biggest challenge is that RISC-V is still perceived as a hobbyist architecture, and this makes it difficult for mainstream companies to adopt, unless it has deep ecosystem support. It’s not enough to have a cool or disruptive technology. Designers need to provide assurances to their customers that a chip or system fits into their existing design flow and toolchains and can be supported, wherever in the world it may be.

This is why the recently appointed CEO of the RISC-V Foundation, Calista Redmond, said at the workshop here in Zurich, “We need to move this past a hobby.” Around 250 or so workshop attendees from both industry and academia, including representatives from Arm, Google, Huawei, NXP, Samsung and STMicroelectronics, listened to a ‘state of the union’ on the architecture, software, tools, debug, verification, and security, as well as numerous ongoing projects and community initiatives.

Redmond is keen to use her experience in open source initiatives to drive the RISC-V Foundation, saying she had the appetite for open source and the timing was right for her to join RISC-V, taking it to a new level. She admitted the market for RISC-V is yet to develop, but that there were a lot of initial silicon RISC-V cores, which were yet to become visible. Almost as if dismissing the hobbyist image, she added, “This is not just an academic project, this is going mainstream.”

Gaining Traction

While you’d expect the main vocal proponents of RISC-V – namely SiFive and Western Digital, and to a certain extent Microchip (which doesn’t shout as loud) to be talking up the values and benefits of the architecture, there were many experienced voices at the workshop who suggested that we are clearly at a watershed moment for RISC-V. Simon Davidmann president and CEO of Imperas, which provides virtual debug and test platforms for embedded systems, said that the company is seeing equal instances of Arm, RISC-V and other architectures in the market, and they are servicing all platforms.

Imperas used the workshop to announce a collaboration with Metrics to help deliver an ‘off-the-shelf’ test and verification solution for RISC-V cores, to help achieve the required tape-out-ready quality for broad adoption by silicon designers. The companies have developed an early stage of this framework using the Google open source Instruction Stream Generator for RISC-V processors and Google cloud services.

Loic Lietar, co-founder and CEO of GreenWaves Technologies, said they are seeing huge interest for its GAP8 processor. “People are screaming for face ID solutions. After that, the next big area of interest is in gesture recognition.” He added the next major market opportunity he sees for the company is in smart toys. The company was recently named in Gartner’s report on cool vendors in AI semiconductors.

Lietar said the AI industry is at an inflection point as the need for interpretation of rich data sources is pushed out into IoT devices operating at the very edge of the network. “We are seeing a clear market need for a flexible processor, optimized for battery operation, incorporating acceleration for AI and other signal processing algorithms to support booming IoT and consumer applications such as medical wearables, and people and object detection and counting.”

Other signals in the market also point to a possible turning point in the RISC-V story. One is the commitment from Qualcomm Ventures to explore the potential of RISC-V in wireless and mobile with its part in the latest $65.4 million funding in SiFive. And there are the many different emerging and evolving groups to support the development of proper support infrastructure for RISC-V architecture. We also saw Andes Technology launch its RISC-V FreeStart program to encourage developers to try using a commercial grade RISC-V CPU core without having to pay any upfront license fees.

ISA Alone is Not Enough

As Lietar highlighted in Zurich this week, “A free instruction set architecture (ISA) is nothing special without the commercial grade tools to support it.” This is why GreenWaves is one of the founding sponsors of the OpenHW Group, a new not-for-profit global organization which aims to boost the adoption of open-source processors by providing a platform for collaboration, creating a focal point for ecosystem development, and offering open-source IP for processor cores. The model they will operate is very similar to the Linaro model and leverages the RI5CY and Ariane open source RISC-V cores from the ETH Zurich PULP platform.

The group is headed and co-founded by Rick O’Connor, who was previously CEO of the RISC-V Foundation. He said the RISC-V Foundation is focused on specifications and not delivery of cores. Hence the OpenHW Group is moving beyond the specs to focus on delivering and supporting proven RISC-V based IP with the ecosystem it needs plus quality and manufacturability assurance. The group’s chairman, Rob Oshana, who is also VP of software engineering at NXP summed it up by saying that industry needs hardened SoCs for wider adoption which is what the OpenHW Group is enabling.

O’Connor explained that the group is aiming to make it easy for high volume semiconductor manufacturers to adopt RISC-V based cores, especially when companies like NXP and Silicon Labs need existence proof for open source IP. “We are not asking them to change their development methodology, but instead use existing design and verification tools,” he said.

He adds, “When we release a core to production, the IP will be a supported piece of IP in the market. For continuity, it will need both internal and external contributors, a roadmap and support infrastructure that the community can rely on – and it’s that whole environment we are providing.

Oshana continued, “The electronics industry is embracing open-source processor technologies at an unprecedented rate. At NXP we believe there’s a need to create a deep ecosystem to support adoption of the RISC-V ISA. This includes various components – middleware, stacks and tools – all aligned to move the architecture forward.”

Another board director, of the OpenHW Group, Alessandro Piovaccari, who is also CTO of Silicon Labs, said many of the billions of SoCs expected to form the smart, connected world in the next few years will contain many specialized cores to address various tasks from subsystems supervision, to security and machine learning. He added, “I believe the CORE-V family of open-source RISC-V cores will be vital in providing robust and accessible processors to address this need, which will ultimately help accelerate innovation in the IoT.”

The OpenHW Group has already recruited 13 sponsor organizations and expects this to grow to 25 by the end of 2019. It is also a member of the RISC-V Foundation and has entered into a strategic partnership with the Eclipse Foundation, a global community for open-source software collaboration and innovation. The inaugural OpenHW sponsors include Alibaba, Bluespec, CMC Microsystems, Embecosm, ETH Zurich (University), GreenWaves, Imperas, Metrics, Mythic AI, NXP, Onespin, Silicon Labs and Thales.

In his state of the union address at the workshop, Krste Asanovic, chairman of the RISC-V Foundation and also cofounder of SiFive, said he expects significant investment in high-end RISC-V implementations in areas like the server, mobile and automotive in 2020. “RISC-V will start taking other sockets on the SoC, such as the DSP, AI, graphics and network processing.”

Asanovic was keen to highlight high-profile users already in market with RISC-V – such as Nvidia, Huami, Google and Fadu. In fact Huami is said to have launched two new smartwatches this week one of which, the Amazfit Bip 2, which uses the Huangshan No. 1 chipset based on RISC-V.

Calista Redmond

In summary, RISC-V is certainly gaining traction but there has been quite some concern among larger established companies of its stability and ecosystem support. The Gartner hype cycle is probably the best way to describe where we are at present with RISC-V: many startup companies, lots of initial projects and early adopters, and lots of media hype.

But events over the last few weeks, like the launch of the OpenHW Group, plus further moves expected in the coming weeks from the Chips Alliance and possibly even more groups means there will be a next phase in the evolution of this open source architecture that attempts to bring some connections between the disruptive architecture (and choice of ISA) that it may present to many, and existing design flows that then make it easier to integrate.

Plus, with funding now coming in with large rounds, like that in SiFive last week, and more large reference customers and early adopters, RISC-V will no doubt start making inroads into more design slots. RISC-V is definitely coming of age.

>> This article was originally published on our sister site, EE Times: “RISC-V Moving Beyond Academia, New Group offers Hardened SoCs.”

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