The third annual RISC-V summit takes place next month, 8-10 December 2020, and like the majority of events this year, will be completely online. The program features three days of talks around architectures, hardware, software, tools, verification and security, plus case studies from the global RISC-V community.
Technology companies and research institutions will share notable product updates, projects and implementations, and discuss the role of the RISC-V instruction set architecture (ISA) in driving next generation of hardware, software and intellectual property (IP). The event will also feature an online exhibition hall and networking opportunities. Speakers include executives from Andes Technology, Alibaba, the CHIPS Alliance, Google, IBM, NXP Semiconductors, OneSpin Solutions, RedHat, Seagate, SiFive, Western Digital and others.
As a media partner, embedded.com will also be participating and we also have a fireside chat that on 9 December 2020 that includes David Patterson, who coined the term reduced instruction set computer (RISC) back in 1980, and who with John Hennessy in 1990 published the textbook, “Computer Architecture: A Quantitative Approach”, which has been a foundational book for many microprocessor engineers since.
The full agenda is online (check out the web site here), but here are some highlights.
Day 1, Tuesday 8 December 2020
Building an Open Edge Machine Learning Ecosystem with RISC-V, Zephyr, TensorFlow Lite Micro and Renode: By moving closer to the edge, machine learning is profoundly changing the IoT landscape. To be able to fully capitalize on the opportunities arising from this trend, an open ecosystem of modern tools, frameworks and platforms is needed that together will constitute a seamless environment for developers to build advanced ML applications on RISC-V. The keynote panel will feature Tim Ansell (Google), Kate Stewart (Zephyr Project), Brian Faith (QuickLogic) and Michael Gielda (Antmicro) in a discussion of how the strengths of RISC-V, Zephyr RTOS, TensorFlow Lite and Renode can be combined to provide collaborative, software-driven, traceable ML development for the very edge. The participants will discuss how the vendor-neutral approach of RISC-V resonates with the foundational principles of the Zephyr RTOS and the Renode simulation framework, and how TensorFlow Lite Micro can leverage the open ISA and its tools to innovate in the ML domain also on the hardware level, e.g. using FPGAs or custom extensions.
Leveraging the RISC-V Eco-System to Put a Chip in Customer Hands in less than $10M: This talk will present the journey of Intensivate in developing the first commercial cluster CPU, with a focus on how the RISC-V ecosystem enables delivering a commercially viable chip, in a 12nm process node, into customer hands at less than $10M. Dean Halle, CEO of Intensivate, will describe the ways in which the cost to deliver such a chip was reduced, including the role that the RISC-V software ecosystem played, the role of the Rocket-Chip RTL available from Chip Yard, the role of FireSim FPGA emulation system, and the role of the Chisel hardware language.
Day 2, Wednesday 9 December 2020
RISC-V in 5G New Radio Small Cell Base Stations: Modern cellular communications use the orthogonal frequency-division multiple access (OFDMA) air interface, in which data is transmitted in symbols which are grouped in slots. In 5G these slots can range from 0.25 and 0.125 ms. The scheduling of the traffic carried in these slots is done by the MAC layer. It schedules traffic to the network (uplink) as well from the network to the user (downlink). Efficient 5G base stations are being designed and deployed to handle not just many, many users supporting many 5G cells but even have support for several separate mobile operators. Each operator may require its own software. The physical layer (PHY) must process the data (both control and user) passed to it by the MAC to fill in the slots and symbols for transmission and reception. If the PHY fails to meet the strict timing constraints whole slots of data will be lost requiring recovery mechanisms. In this talk, Gajinder Panesar (Mentor, A Siemens Business) and Peter Claydon (Picocom) present a heterogeneous SoC which implements a 5G NG small cell base station using clusters of RISC-Vs and dedicated DSPs. The talk will also show how the strict timing constraints are continuously monitored non-intrusively and how embedded analytics provides useful insights into the behavior of the base station.
Secure IoT Firmware for RISC-V: Over time, established platform vendors have developed lightweight Trusted Execution Environments (TEEs) and relative embedded software stacks optimized for their smaller processors. However, none of these are available to RISC-V developers who are left alone figuring out how to shield trusted code from unverified 3rd party software libraries and how to safely combine these components into the single firmware image powering their commercial applications. In this presentation, Cesare Garlati (Hex Five Security) and Sandro Pinto (Universidade do Minho) will introduce a free and open secure IoT stack for RISC-V, covering all hardware and software components necessary to build state-of-the-art device, firmware, and cloud management service. These include RISC-V 32-bit SoC FPGA, multi-zone Trusted Execution Environment, safety-critical RTOS, TCP/IP connectivity, TLS ECC cryptography, and MQTT client and broker providing telemetry and OTA applications deployment and firmware updates.
Day 3, Thursday 10 December 2020
Embedded Software Reimagined: Thread Processors Implemented Using RISC-V: As system complexity increases, it becomes more difficult to configure an RTOS to meet all possible operating scenarios. Developers must ensure that priority inversions, deadlocks, resource contention, race conditions, and other timing related problems cannot occur, regardless of the operating conditions of the system. Despite detailed analysis and rigorous verification, many design teams will select a larger and more powerful processor than is really needed to provide a margin of safety against unforeseen circumstances. An alternative is to assign each task to its own CPU core. This dramatically simplifies many of the scheduling and real-time issues around managing a collection of tasks. With the configurability and efficiency of RISC-V cores it is both possible and practical select and configure a core for a specific task, run just that task on the core, and power it down when the task is not active. Russell Klein (Mentor Graphics) and Colin Walls (Mentor, A Siemens Business) illustrate this concept using an example design that has both high and low compute complexity tasks, both with and without hard real-time constraints. To address the issue of practicality, power, performance, and area (PPA) metrics for the exemplary system implemented in a 14 nm ASIC library are given.
A Guide to the RISC-V Cryptography Extension: Ben Marshall (University of Bristol) and Barry Spinney (Nvidia), give a tour of the RISC-V cryptography extension, explaining how it caters for every class of core: from deeply embedded to large servers. They will explain the new instructions and how they should be used, along with expected implementation costs and software performance improvements.
CORE-V-VERIF, an Industrial-Grade Verification Platform for RISC-V cores: CORE-V-VERIF provides a silicon-proven, industrial-grade functional verification platform to the RISC-V community. The platform has been used to execute a complete verification cycle of the CV32E40P core and is currently being used to execute verification of the CV32A6 and CV64A6 cores. CORE-V-VERIF leverage verification components developed by the RISC-V community and will be continuously maintained and enhanced to integrate the latest best-practices and technology for the verification of future CORE-V cores. This session delivered by Sven Byer (OneSpin Solutions), Steve Richmond (Silicon Labs) and Mike Thompson (OpenHW Group) includes an in-depth analysis of the CORE-V-VERIF platform, and a quick-start training to deploy the platform in RISC-V verification projects. Silicon Labs, which is integrating CORE-V cores into IoT chips, shares its view of why verification is crucial to take open-source hardware to the next step.
To sign up to the 2020 Virtual RISC-V Summit, December 8 – 10, and take part in the three-day program packed with keynotes, technical presentations, tech talks, tutorials and more focusing on the future of RISC-V and the larger semiconductor industry, check out the website and register here.
- Taking the mystery out of custom extensions in RISC-V SoC design
- Telink SoC uses RISC-V P-extension for AI/ML on edge devices
- Imperas extends RISC-V reference simulator for coverage driven verification analysis
- New Renesas ASSPs based on Andes RISC-V to sample in 2021
- RISC-V speaks on options after Nvidia-Arm news
- Microchip launches $500 RISC-V based FPGA development kit
- Extending the RISC-V architecture with domain specific accelerators
- Don’t let baggage hinder innovation: RISC-V lets us start with a clean slate
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