Samplify runs APAX IP on Cortex-A9s with Xilinx Zynq -

Samplify runs APAX IP on Cortex-A9s with Xilinx Zynq

At the ARM Technical Conference in San Jose, Ca., Samplify ran a demonstation of its new APAX intellectual property (IP)  running on two ARM Cortex-A9 processors in the Xilinx Zynq Extensible Processor Platform.

Samplify designed the APAX IP to accelerate throughput of memory, I/O, and storage by 2X to 8X for high-performance computing (HPC) and cloud computing, as well as consumer electronics and mobile devices performing applications such as image acquisition, video processing, and 3D graphics.

“Multi-core CPUs are hitting the memory wall,” said Al Wegener, CTO and founder of Samplify. “With each new process node, the number of processor cores on a die can double with Moore's Law, but the throughput of memory, I/O, and storage fails to keep up with this growth. Hence, the performance of multi-core applications is increasingly memory, I/O, and storage bound.

The APAX IP includes a universal numerical data encoder that operates on all integer or floating-point data types, as well as images and wireframe meshes. APAX achieves typical encoding rates of 2:1 to 8:1 without affecting the results of computing or imaging applications.

The low-complexity APAX IP core supports an industry-standard AXI bus interface, serving multiple clients in an SoC or motherboard chipset: the memory controller, the flash or disk storage controller, and the I/O controller.

According to Wegener, the low latency of the APAX IP core even makes it suitable for implementation between Level 3 and Level 2 cache. The APAX IP core is fully compatible with APAX software products, and the included Linux software driver allows seamless switching between HW and SW implementations of the APAX encoder and decoder.

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