Sarnoff offers H.264 Video on MIPS architecture - Embedded.com

Sarnoff offers H.264 Video on MIPS architecture

MANHASSET, N.Y. — MIPS Technologies and Sarnoff Corp. today announced that Sarnoff will offer its latest H.264 codecs on the industry-standard MIPS architecture.The offering enables MIPS Technologies (Mountain View, Calif.) to provide its customers a broad range of video solutions, using the MIPS architecture to encode, decode, and display vivid, high-resolution, full-motion video for television, teleconferences, movies, camcorder features, music videos and other business and entertainment applications.The codecs, part of Sarnoff's line of SelectCores silicon IP, can accommodate video at up to 30 frames/second and up to VGA resolution (640 x 480). They are compatible with the ITU H.264 and MPEG-4/AVC standards. Included hardware-based accelerators may be implemented to maximize flexibility. Software-only codecs are also available, optimized for the MIPS instruction set.”The MIPS architecture is the de facto standard in many digital consumer applications that would benefit from intensive video decoding, and we're delighted to support these cores with our codecs,” said Bill Mayweather, senior director, IC systems and services at Sarnoff. “Chip designers now have ready access to a highly efficient implementation of H.264 technology that combines design flexibility and the highest quality video with the lowest power consumption.”

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