Saving your embedded printed circuit board design with forensic technology - Embedded.com

Saving your embedded printed circuit board design with forensic technology

Continually shrinking printed circuit boards (PCBs) populated with greater numbers of package-on-package (PoP) devices have made it tougher for design engineers to locate causes of system failures. After spending many hours or days trying to uncover design defects and flaws using traditional methods such as automated optical inspection (AOI) or x-ray, design engineers may simply give up and discard their designs, losing the time and considerable money they’ve invested in them, simply because they cannot locate the culprit making their designs inoperable.

(AOI) or x-ray are highly reliable tools for conventional inspection but they aren’t always able to detect elusive defects such as a micro hairline fracture within a solder joint, as shown in Figure 1, or black pad or minute solder pin holes not seen at the 300 or 400 magnification level.

Figure 1: Micro hairline fracture within a solder joint

Forensics to the rescue
Forensic technology may succeed where conventional inspection fails, in particular with advanced technologies like PoP. Board forensics using inspection kits consisting of scanning electron microscopes (SEM) and time domain reflectometry (TDR) are key sleuthing tools.

Figure 2 shows an impedance control chart with 90 ohms impedance shown on a TDR report with a 5 percent tolerance.

Figure 2: 90 ohms impedance shown on a TDR report with 5% tolerance

Forensic tools and techniques provide the microscopic detective work and uncover a variety of tiny design or manufacturing problems that automated optical inspection (AOI) or x-ray may miss.

Designing to avoid use of forensics
Embedded systems designers are faced with a myriad of new challenges posed by continually shrinking boards and advanced component packaging, like PoP.

One such area is 0.3 mm ultra-fine ball grid array (BGA) pitch design. In this case, as of this writing, there are no Association Connecting Electronics Industries IPC standards or guidelines for ultra-fine BGA pitch levels below 0.5 mm pitch. So, the savvy PCB designer pulls from his or her bag of tricks to perform the most efficient design possible.

Part of that is keeping in mind that land patterns are especially tight. The PCB designer knows that only one set of traces can go between the pads of these ultra-fine pitch BGA devices. But if two are used, manufacturing issues arise. Moreover, it’s critical for the PCB designer to assure the fabrication house has the necessary leading-edge technology to deal with a high-caliber board that supports ultra-fine BGA pitch below 0.5 mm.

Stringent control of a design’s transmit and return path is another key consideration. It should be as short as possible. The last thing the PCB designer wants is to create ripples in transmission and reception. Therefore, the tolerances of those impedance control traces should be extremely tightly matched. Tolerance should be within one to two percent with a five percent maximum. This creates a very clean eye diagram and keeps signal to noise ratios (SNRs) under control once the design is completed and undergoes simulation.

The PCB designer also has to take into account the fact that boards are not only getting smaller, but thinner. Earlier, the industry dealt with 62 mil thickness boards; now, providers are working with 47 and 31 mil and even thinner boards. The role the PCB designer plays in this case is to accurately define a panel size for small boards to assure optimal printing and placement.

Testing also becomes more challenging with these designs. For one, test pad points are shrinking. Therefore, finer test points must be defined to assure they are proper for flying probe or in-circuit test (ICT). These test points should be big enough to accommodate the probing of flying probe test, yet small enough relative to the size of an ever-shrinking board. The question for the PCB designer is where to place test points. Should they go on the component side where all the decoupling capacitors are connected or on the bottom side of the BGA?  Considering that everything is shrinking – the board and packaging – test points are placed on the bottom side of the BGA most of the time since there’s little real estate left.

This also means creativity plays a major role in these designs. Instead of testing individual components at one time, like before, the PCB designer now has to design in a method whereby a module of the circuit can be tested from few test point locations; thereby the need of a vast number of test points is greatly reduced.

A further challenge is that passives continue to become dramatically smaller. For example, the newest 01005 package is half the size of the 2001, which is about the size of a grain of salt. The 01005 has to be machine placed; otherwise, there’s no other way for it to be placed on a board or to be reworked at a later stage.

Forensics: the big spy glass for tiny defects
If there’s anerror or miscue after a design is complete and dispatched to assemblyand manufacturing, forensics can uncover issues that traditionalinspection passed.

Forensics is better known as “destructiveinspection.” It’s destructive because a completed designed and assembledboard is sacrificed and sliced open along with its component populationso that inspectors can peer inside it via SEM and/or cross sectionimage to start their detective work. Cross sectioning (Figure 3 ) is amain player in this failure analysis. It provides the physical evidenceof the failure mode and site location, as well as isolates suspectedversus non-suspected devices.

Figure3: Cross-sectioning provides the physical evidence of failure mode andsite location, as well as isolates suspected versus non-suspecteddevices.

There are innumerable failurepossibilities to check out. Forensics can take an extremely close uplook at inter-metallic failures, for example. Those are the mosttroublesome when it comes to BGAs, meaning those failures create whatare known as “intermittent connections”.

Forensics also takes agood look at solder thermal fatigue when testing for solder jointfailure. Solder thermal fatigue occurs in the field when the product isused in excessive heat, especially when it contains BGAs or flip chipdevices.

Those fatigue cracks begin slowly and over time thesolder gets detached from the surface of the board due to the excessiveheat. This is especially true if the BGA isn’t designed properly or ifit’s an analog circuit and heat dissipation isn’t incorporated in theboard design. In some cases, there can exist a coefficient of thermalexpansion (CTE) mismatch between packages that contributes to thisfailure.

Sometimes the non-destructive tools, traditional AOI andx-ray, may not identify all solder fatigue. For instance, the failureor failures could be due to solder joint detachment and even tin whiskergrowth, which at times AOI and x-ray don’t recognize, because it isdeveloped over time and may not be present at the time of initialassembly.

In some cases, the solder bridging of flip chip deviceshas leakage failures. Due to solder or flux, especially when the deviceuses underfill, a flip chip device leaks current after thermalcycling. Therefore, current doesn’t get to the proper ball of the BGAand a non-acceptable noise creeps into the design at certainlevels. Destructive analysis or forensics via SEM can reveal the voidsdue to the fact that air gaps are created inside the solder due to poorplating, as shown in Figure 4 .

Figure 4: SEM reveals voids due to air gaps created inside the solder due to poor plating.

Afterthermal cycling, a high-powered optical microscope can be used toverify other issues, such as de-lamination or bulk solder extrusion. As aresult of thermal cycling, a solder can leak out to such areas as vias,thereby reducing the amount of solder needed to optimize a BGA’s solderjoint.

Conventional inspection
There is stillconsiderable merit to applying AOI and x-ray inspections. Think ofconventional and forensics inspection as a double-barreled solution tocatch defects and flaws. Today's PCB technologies demand the mostadvanced systems possible to get even closer to those design ormanufacturing issues stemming from state-of-the-art packaging andshrinking PCBs.

AOI is a smart machine fitted with either four orsix cameras, with side angle viewing to capture specific images likeetch marks on a component. It catches problems like wrong polarity,missing or wrong components, wrong-orientation component placement, andwrong packaging. It detects whether a generic component was used insteadof one supplied by the OEM customer. AOI is programmed along with the“golden board,” which is the ideal and perfect board coming off theassembly line. Once that’s done, it’s used to compare it with otherboards.

Two types of x-ray are standard and automated x-rayinspection (AXI). AXI is more advanced and adept at dealing withleading-edge packages like BGAs, CSPs, flip chips, QFNs, DFNs, andothers. It can detect such defects as head-on-pillow, disjointed balls,and wire bonding damage, using automated AXI features. Plus, AXIperforms highly efficient void analysis. It calculates voids by volumeor by size and provides the 'go' or 'no go' depending on how the processwas performed.

To recap, even as the industry moves to smallerform factors and three to four packages are mounted on top of eachother, OEM concern over maintaining high reliability for their systemsand sub-systems is considerably alleviated thanks to both conventionaland forensics inspections.

Zulki Khan is the Founderand President of NexLogic Technologies, Inc., San Jose, CA, an ISO9001:2008 Certified Company, ISO 13485 certified for medicalelectronics, and a RoHS compliant EMS provider. Prior to NexLogic, hewas General Manager for Imagineering, Inc., Schaumburg, IL. He has alsoworked on high-speed PCB designs with signal integrity analysis. Heholds B.S.E.E from N.E.D University and M.B.A from University of Iowaand is a frequent author of contributed articles to EMS industrypublications.

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