Santa Cruz, Calif. — If you want an easy way to design chips, says consultant Jan Decaluwe, look no further than the Python scripting language. Python can be turned into a hardware description language (HDL) with the help of Decaluwe's open-source tool suite, MyHDL.
Decaluwe, a design consultant based in Leuven, Belgium, was a founder of Easics BV, a design services firm that offered a hardware/software synthesis tool in the late 1990s. He's still a director of Easics, which Transwitch Corp. acquired in 2000 and more recently spun back out. But much of his work during the past few years has been the single-handed creation of MyHDL.
“At Easics, we had been using many different scripting languages, and finally we discovered Python,” Decaluwe said. “Python is the most brilliantly designed language I know of. When I left Easics, I thought, 'Wouldn't it be nice to use [it] to do hardware design work?' “
Available for free download at http://myhdl.jandecaluwe.com, MyHDL is essentially a Python package that makes it possible to use the language as an HDL or a hardware verification language. It includes a simulation capability and a recently developed Python-to-Verilog converter.
Why offer all this hard work for free? “In software engineering, I can get all of these wonderful tools developed by brilliant people for free,” Decaluwe said. “In some cases, the real innovation occurs in the open-source world. I really believe hardware design has the potential to become just another software-engineering process.”
MyHDL is logging around 20 downloads per day. “I now have users taking Python to FPGAs,” Decaluwe said. “I hope we are now in an acceleration phase. At this point, the tool is mature enough to promote it more.”
The key idea behind MyHDL, Decaluwe noted, is the use of Python “generators” to model hardware concurrency. Generators can be described as resumable functions. They're similar to Verilog “always” blocks and VHDL processes, Decaluwe said.
MyHDL provides a Python package that allows generators to communicate. It includes an object used to do bit-oriented operations. A built-in simulator runs on top of the Python interpreter. Finally, to “close the loop,” Decaluwe wrote the Python-to-Verilog converter.
“It's not a behavioral-synthesis tool, but it is more intelligent than just a translator,” Decaluwe said. For example, he noted, MyHDL supports enumerated types. By adding different attributes to enumerated types, a MyHDL user can automatically change the encoding of a state machine in the translated Verilog.
The converter also supports signed arithmetic, which, said Decaluwe, is a “nightmare” in Verilog. “If you're not careful, everything is done unsigned,” he said. “These issues do not exist in MyHDL. The translator takes care of these things automatically, and can add a signed bit when it's necessary. Verilog users should start taking a look at this, because some of the tasks they face are much harder to do in Verilog directly than they would be in MyHDL.”
While Python can be used as a full-fledged HDL, Decaluwe said, it's unrealistic to expect the big EDA vendors to come out with Python synthesis tools. Hence the need for a conversion to Verilog. Because of the need for implementation, he said, MyHDL focuses on RTL design, even though Python could be used at a much higher level of abstraction. “What I hope will happen is that people will realize they have all these capabilities in Python, and they can use this to create really high-level models,” he said. Testbenches can be written at a high level, Decaluwe noted, and MyHDL models can be co-simulated with traditional HDL models.
The MyHDL simulation capability, meanwhile, supports the concept of “unit testing,” which is widely used in software development. It basically means that tests are written immediately for any hardware module that's developed, however small. An element such as a finite state machine would thus be thoroughly verified before being integrated into the larger system.
Decaluwe said that students, faculty and professional design consultancies are using MyHDL. Based on user feedback, he recently added RAM and ROM inferencing features for Xilinx FPGA designers.
“I don't want this to be an academic exercise,” Decaluwe said. “The goal is to have it be used by real engineers to solve real problems in the industry.”