ProASICPlus is Actel's second-generation family of flash-based field-programmable gate arrays (FPGAs). The in-system programmable family includes six devices ranging in density from 150,000 to 1-million system gates.
They combine a fine-grained, ASIC-like architecture and non-volatile flash configuration memory. The devices are live at power up, highly secure and require no separate configuration memory, all characteristics shared by ASICs.
The ranges architecture supports ASIC tool flows (see box), which should reduce design-in time and enable migration between FPGA and ASIC solutions.
This generation adds multiple phase-locked loops (PLLs), support for up to 198kbits of two-port embedded SRAM and 712 user-configurable I/Os, and improved in-system programmability.
The ProASICPlus devices have system speeds of up to 100MHz and allow seamlessly interfacing between 3.3 and 2.5V devices in a mixed-voltage environment. The family contains two advanced clock-conditioning blocks, each consisting of a PLL core, delay lines and clock multiplier/dividers.
Additionally, two high-speed LVPECL differential input pairs accommodate clock or data inputs. In-system programmability is supported through the IEEE standard 1149.1 JTAG interface.
ProASICPlus FPGAs are user programmed with a multi-bit key that blocks external attempts to read or alter the configuration settings. Decapping and stripping of the device reveals only the structure of the flash cell, not the contents. This level of design security is better that beyond SRAM-based FPGAs and conventional ASIC solutions say Actel and might provide a new business model for intellectual property providers.
The devices have up to 198kbits of 2port SRAM and up to 712 user I/Os which provide 50MHz PCI performance. The non-volatility and reprogrammabilty are through use of a Flash-based 0.22 LVCMOS process with four layer metal. Standard CMOS design techniques are used to implement logic and control functions including the PPLs and their associated circuitry such as LVPECL inputs.
The device's core consists of a Sea-of-Tiles and each tile can be configured into any 3-input/1-output logic function (except a 3 input XOR), flip-flop or latch by programming the appropriate Flash switches.
The combination of the fine granularity, flexible routing resources and the number of flash switches are said to provide up to 100% untilisation and 95% routability for highly congested designs.
Gates and larger functions are interconnected through a 4-level routing hierarchy. Embedded 2-port SRAM blocks with built-in FIFO/RAM control logic can programmed for synchronous or asynchronous operation, as well as parity generations or checking.
The clock conditioning circuitry is based on two clock conditioning blocks, each with a PLL core, delay lines, phase shifts (90, 180, 270), and clock multipliers/dividers. This is all the circuitry needed to provide bidirectional access to the PLL, and operation upto 240MHz. The PLL block contains four programmable frequency dividers which allow the incoming clock signal to be divided by a range of factors of up to 64.
The clock conditioning circuit will also delay or advance the up to 4ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL there are two LVPECL differential input pairs to accommodate high speed clock and data inputs.
The routing structure of the ProASICPlus devices is designed to provide performance through a flexible four-level hierarchy of routing resources: ultra fast local resources, efficient long line resources, high speed very long line resources, and high performance global networks.
The ultra fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles.
The efficient long line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPlus device.
Each tile can drive signals onto the efficient long line resources, which can, in turn, access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout.
The high speed very long line resources which span the entire device with minimal delay, are used to route very long or very high fanout nets. The routing software automatically inserts active buffers to limit loading effects due to distance and fanout.The high performance global networks are low skew, high fanout nets that are accessible from external pins or from internal logic. These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input on all tiles.Each device has four power and delay friendly global clock trees. Each is based on a network of spines and ribs that reach all the tiles in their regions. This flexible clock tree architecture enables mapping of up to 56 different internal/external clocks.
Using existing design flows
The family makes use of Actel's Designer software, which includes place-and-route, timing analysis and memory generation functionality. The devices are also supported by third-party design tools from suppliers including Cadence, Exemplar, Model Technology, and Synopsys.
Because the ProASICPlus devices work equally well with ASIC and FPGA design methodologies, designers can create high-density systems using existing tools and flows.
Synplicity's Synplify software products have been optimised for use with the FPGAs. It performs technology mapping of HDL-based designs directly into the ProASICPlus devices. The software will allow forward-annotation of design constraints to achieve peak place-and-route results.
Mentor's LeonardoSpectrum synthesis tool provides push-button and incremental methodologies with optimisation and technology mapping of HDL designs to architecture-specific resources in the ProASICPlus devices as well as TimeCloser technology for rapid timing closure.
Published in Embedded Systems (Europe) February 2002