Segger J-Link supports Silicon Labs 8051 devices

SEGGER has added support for Silicon Labs’ 8051 family of 8-bit microcontrollers (MCUs) to its J-Link family of debug probes. This includes run control as well as download into RAM and Flash of all supported devices.

J-Link offers high debug and download performance into RAM and flash memory on all supported targets, now including debugging 8051 devices. SEGGER supports 32-bit architectures like ARM, MIPS and RX cores, and also 8-bit architectures.

The SEGGER J-Link is tool chain independent and works with free GDB-based tool chains such as emIDE and Eclipse, as well as commercial IDEs from: Atmel, Atollic, Coocox, Cosmic, Freescale, IAR, KEIL, Mentor Graphics, Microchip, Python, Rowley, Renesas, Tasking and others. Investments in the debug probe are preserved when changing compiler or even CPU architecture.

J-Link supports multiple CPU families, such as ARM 7, 9, 11, Cortex-M, Cortex-R, Cortex-A as well as Microchip PIC32, and Renesas RX100, RX200, RX600, and 8051; there is no need to buy a new J-Link or new license when switching to a different yet supported CPU family or tool-chain. SEGGER continuously adds support for additional cores, which in most cases only requires a software/firmware update. Unlimited free updates are included with even the baseline model of the J-Link family. All J-Links are fully compatible to each other, so an upgrade from a lower-end model to a higher-end model is a matter of a simple plug-and-play.

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