Mass storage densities are in an unprecedented state of growth inembedded applications. Consumer devices such as portable media players,cellular phones, digital still cameras, portable navigation devices,air cards, and thumb drives are requiring higher densities of massstorage due to widespread demand for increased multimedia capacity.
NAND flash has become theprevalent choice for mass storage in consumer applications due to itslower cost per bit and higher density advantages over NOR Flash, as well as itssmaller size, power, and robustness advantages over Hard Disk Drives.
Because demands are so high for NAND flash in the consumer market,storage prices are decreasing dramatically and other devices such aspoint of sale (POS) terminals, printers, and other applications, cantake advantage and use higher density storage at these lower costs.
However, as the demand for increased NAND flash density surges inthese embedded applications, designers are faced with the challenge ofselecting from a variety of NAND flash types, densities, vendors, androadmaps as well as implementations.
The first and most important selection criterion for using NANDflash is the implementation of the NAND controller. All NAND flashdevices require maintenance overhead located in the software andhardware of an external controller to ensure reliable data, maximizethe lifespan of the NAND flash device and to enhance performance. Thethree main functions of the NAND controller are Bad Block Management,Wear-Leveling, and Error Correction Coding (ECC).
NAND flash stores memory in clusters called blocks. Most NAND flashdevices will inherently be built with some bad blocks that will befound upon testing conducted during manufacturing, and these blockswill be labeled as bad in the device specification by the vendor.
In addition, good blocks may degrade over the life cycle of the NANDand must be tracked via software, aka, Bad Block Management.Additionally, consistent reads and writes to a particular block maycause the block to “wear out” and become a bad block. In order toensure maximum life of the NAND and limit the amount of blocks thatwear out, all blocks should be read and written to evenly in a processcalled Wear-Leveling.
Finally, bit errors may occur due to inactivity or operation of aparticular cell and ECC must be implemented in either software orhardware to detect and correct these errors. ECC is typically definedby the industry as the number of bits the code can correct per 528-bytesector. In a system, this NAND controller can be combined with the NANDin the three different configurations as shown in Figure 1 below .
|Figure1: NAND Architectural Options|
In conjunction with selecting from the three options of NANDsolutions shown in Figure 1 above ,a designer must also choose between two types of NAND flash devices,SLC (Single-Level Cell) NAND and MLC (Multi-Level Cell) NAND, each ofwhich offers its own benefits.
SLC NAND provides longer life cycle and reliability of each block,therefore requiring less ECC and offering superior performance. MLCNAND offers less performance and is more difficult to implement sinceit requires higher levels of bad block management, wear-leveling andECC.
However, it is also roughly 1/3rd of the price of SLC NAND per bit.Because of the increasing differential of cost between SLC and MLCNAND, most applications are moving to MLC NAND, especially in higherdensity type applications, in order to substantially decrease bill ofmaterial costs.
The selection of one of the three options in Figure 1above is based upon multiplefactors including Microprocessor NAND controller support, the type ofNAND being used (SLC or MLC), and the density of NAND required on theplatform.
In platforms where designers are using a Microprocessor that has afull NAND interface and controller, Option 1 is typically the preferredchoice. Most contemporary microprocessors, if they have any support forNAND at all, typically only support SLC NAND in lower densities.
The process technology limits the amount of storage on a die of SLCor MLC NAND, as currently this density is at about one gigabyte ofstorage per die. Therefore, in order to support higher densities ofNAND, a controller must be able to support multiple NANDs.
This is usually done using an interleaving process and multiplechip-enables. The addition of multiple chip-enables to support multipleNANDs can drive the pin count of a microprocessor higher, which makesinclusion of this type of NAND controller into the microprocessor lessprevalent.
Also, the MLC NAND interface is very rarely seen on microprocessorsfor a number of reasons. As process technologies nodes of MLC NAND movelower, the levels of Error Correction Coding required to support thistype of NAND become higher.
Currently, the levels of ECC needed for MLC NAND are at 4-bit, butare quickly moving to 8- and 12-bit. The higher amounts of ECC requirehardware in the NAND controller. However, microprocessor evolution isproceeding at a slower pace than the rapidly evolving MLC NAND.
The “Controlled NAND” approach (Option 2) is useful with manydifferent embedded and removable types of storage. All portable SD/MMCcards use this type of implementation, and there are several choicesfor embedded controlled NANDs in the marketplace. This approach has itsadvantages as the Microprocessor only needs to support an SD/MMC typeinterface to add system support for either SLC or MLC NAND.
The controller is stacked with the NAND and handles all Bad BlockManagement, Wear-Leveling, and ECC for the NAND. Controlled NANDimplementations are seen currently at roughly 4 Gigabyte densities inembedded applications and at 8 Gigabyte in removable cards.
The disadvantage with this approach is that each NAND vendorsupports different interfaces on their variety of controlled NAND (onemay use SD, one may use MMC, another may have a proprietary interface),and switching from one NAND vendor to another requires a completesoftware overhaul.
Option 3 gives designers the most flexibility in choosing the typeof NAND as well as in choosing from different vendors. Almost all NANDcontrollers support different types, vendors, and densities of NANDs,and because the NAND controller will always utilize the same interfaceto the processor, the designer is free to choose different types andvendors of NAND without having to change any software.
The block diagram shown in Figure2 below shows a West Bridgeimplementation using a multimedia mass storage controller with fullSLC and MLC NAND management.
|Figure2: Cypress' Astoria Device Implementing West Bridge Approach|
Using a West Bridge interface ” similar in nature and purpose to theNorth and bridges used in PC designs ” supports multiple processorinterfaces such as SRAM, ADMUX, SPI, and NAND and up to 16 SLC or MLCNAND devices from any NAND vendor with 4-bit ECC.
This gives designers the flexibility of choice regarding density aswell as the ability to change NAND vendors on the fly with little to nosoftware changes on the microprocessor. Using an external NANDcontroller can also provide other benefits.
For instance, a West Bridge that supports a High-Speed USB interfacecan bypass the main processor and provide a direct path to mass storagefrom a PC in applications such as portable media players and handsets,giving optimal sideloading performance. Support for SD, MMC, and SDIOinterfaces also enables designers to connect an SDIO type device suchas WiFi, or Bluetooth if the system's microprocessor is limited on SDIOinterfaces.
When considering the combination of requirements for a system's NANDbudget, including density, cost, size, and flexibility, designers haveseveral NAND implementation options, each with its own benefits anddisadvantages. If the system microprocessor has a built-in SLC or MLCNAND controller, no external device or logic is required.
Otherwise, a controlled NAND approach can be beneficial since it ispackaged by the NAND vendor and also requires no external logic orchip. However, for the most flexibility, developers will utilize anexternal NAND controller to support all NAND types and flavors. Thisapproach also provides additional benefits such as performance andinterfaces, but does require an external chip to do so.
Stephen Harris is a product manager at Cypress Semiconductor Corp.