Microchip Technology Inc. has claimed the industry’s first commercially available serial memory controller, while marking its entry into the memory infrastructure market. The SMC 1000 8x25G for data center computing enables CPUs and other compute SoCs to use four times the memory channels of parallel attached DDR4 DRAM in the same package footprint. New CPUs require more memory channels to deliver higher memory bandwidth as the computational demands of artificial intelligence (AI) and machine learning workloads grow.
The SMC 1000 8x25G interfaces to the CPU via 8-bit Open Memory Interface (OMI)-compliant 25 Gbits/s lanes, and bridges to memory via a 72-bit DDR4 3200 interface. This reduces the required number of host CPU or SoC pins per DDR4 memory channel, allowing for more memory channels, while increasing the memory bandwidth available, said Microchip.
A CPU or SoC with OMI support can use a range of media types with different cost, power, and performance metrics without having to integrate a unique memory controller for each type, said Microchip. Typically, CPU and SoC memory interfaces are locked to specific DDR interface protocols. The SMC 1000 8x25G is Microchip’s first memory infrastructure product that enables the media-independent OMI interface.
The SMC 1000 8x25G also delivers a low latency design that provides less than four ns incremental latency over a traditional integrated DDR controller with LRDIMM. This means the OMI-based DDIMM products have nearly the same bandwidth and latency performance of comparable LRDIMM products.
SMC 1000 8x25G samples are available now. For customers building systems that are compliant with the OMI standard, the SMC 1000 comes with design-in collateral and ChipLink diagnostic tools.
>> This article was originally published on our sister site, Electronic Products:”Serial memory controller designed for AI and machine learning workloads.”