Seven ways to avoid embedded PCB engineering change orders - Embedded.com

Seven ways to avoid embedded PCB engineering change orders

Engineering change orders (ECOs) drive up design costs and result in numerous delays in product development that in turn result in costly extension of time to market. However, most ECOs can be avoided by paying careful attention to seven critical areas where problems frequently occur: component selection, memory, moisture sensitivity levels (MSL), design for test (DFT), cooling methodologies, heat sinks, and coefficient of thermal expansion (CTE).

Component Selection
A meticulous review of all a component’s specifications is crucial to avoid ECOs. Initially the PCB designer may routinely check out electrical and engineering data as well as end of life and availability. But when a component is in the early stages of market introduction, all the critical specifications may not yet be available on the data sheet. The reliability data currently available may not be extensive or sufficiently detailed when the component has been on the market for only a few months or is available only in small sample quantities. Consequently, there may not be a sufficient amount of reliability and quality assurance data on field failures, for example.

It’s important not to accept the spec sheet at face value, but to contact the component vendor to learn as much as possible about a component’s characteristics and how these characteristics relate to the design.

An example is the expected maximum current flow or voltage the component will need to handle. If the component is not selected for sufficient current or voltage, the component may burn out. A burned capacitor as shown in Figure 1 .

Figure 1: Considerable current or voltage flowing through the circuitry due to poor component selection can result in damage like this burned capacitor.

Let’s take another example, a land grid array (LGA) packaged device. In addition to electrical and mechanical constraints, you may need to consider the kind of solder paste recommended, the allowed or not allowed reflow temperatures, and the allowed levels of solder joint voiding.

There is no specific IPC standard for voiding criteria associated with devices like LGAs. In some cases, LGA devices with voiding levels up to of 30 percent have been reliable to date. However, generally speaking, lower voiding levels of 25 percent maximum are better and 20 percent is better yet. Figure 2 shows a solder ball with a 20.41% void, which is acceptable for IPC Class II.

Figure 2: Solder ball with a 20.41% void is acceptable for IPC Class II.

In the absence of void data, design engineers have to rely on their experience, know how, and common sense to assure they can perform their designs with easy-to-find components that aren’t at an end-of-life cycle and that are available from multiple sources.

Performing extra analysis and calculations is also highly important in component selection, for instance, calculating current or voltage during peak performance. A component might be specified at a certain peak temperature and current level. However, when it comes to a particular design, the PCB designer must take the initiative to assure that he or she is the one making these critical calculations.

The responsibility rests with the engineer to not only perform calculations on a single component, but consider that component’s relation to other components used in that particular design. For example, calculations are especially important for analog components generating a high level of heat. Let’s say a number of analog components are placed next to each other on one side of the board. Those are creating considerably more power and thereby generate more heat compared to the other side of the board, which is digital in nature. In such a case there is a possibility of solder mask de-lamination occurring on the heavily populated analog component side.

Analog portions of the component’s circuitry can generate a lot of heat. Overheating can create delaminating of the solder mask or in a worst case scenario, it could burn and damage the components. Figure 3 shows board de-lamination.

Figure 3: Poor heat dissipation can lead to PCB de-lamination.

Design and layout engineers need to work together on component placementat the layout stage to avoid placing the component too close to theboard’s edge or next to another component without allowing sufficientspacing. Component placement can be easily designed on the computer, butif component footprints are not created accurately in layout, the pickand place machine might not be able to place them perfectly next to eachother. For example, Figure 4 shows a component protruding slightly fromthe board.

Figure 4: The edge of a connector is shown protruding slightly from the edge of a board.

Thesame principles hold true for memory selection. With the constantemergence of new generations of more advanced DRAMs and flash, the PCBdesigner is challenged to stay ahead of the technology curve anddetermine how ever-changing memory specs affect newer designs.

Forexample, DDR2 generation DRAMs differ from today’s DDR3 devices andDDR3 devices will differ from tomorrow’s DDR4 DRAMs. As of this writing,JEDEC has already announced publication of the DDR4 Standard,JESD79-4. According to market research firm iSuppli, DDR3 DRAM accountsfor 85 to 90 percent of the current DRAM market. However, it predictsthat DDR4 will emerge with a 12 percent share in 2014 and will mushroomto 56 percent by 2015.

PCB designers need to keep a close eye onDDR4’s rise and work with OEM customers as they map out theirnext-generation embedded systems to include DDR4 DRAMs. They must get agood handle on the new features and functions to avoid designcomplacency and subsequent ECOs. Another thing to keep in mind is thatmemory pricing can fluctuate.

Moisture Sensitivity Level (MSL)
Moisturesensitivity level (MSL) is easily overlooked. If an OEM doesn’t factorin MSL in a design and the critical MSL specifications aren’t properlycalled out, then there is a possibility that the CM house won’t take theMSL information into account and circuitry will not work properly inthe field. This is especially true if MSL levels like 3, 4, or 5exist. As a result, baking might not be properly performed and moisturemight creep in, resulting in ECOs. Where LGAs are involved, the PCBassembly house will have to replace those packages on the PCBs. Figure 5is an MSL label for components with Level 5 sensitivity along with sealdate and baking guidelines.

Figure 5: MSL label for components with Level 5 sensitivity along with seal date and baking guidelines.

Design for Test
Designfor test (DFT) is critical for production runs when PCBs undergo testand debug. When placing components on a board, it is important to payclose attention to the placement of DFT probing points and the angle atwhich the probe comes in to touch vias, pads, and other test points.

WhenDFT has not been allowed for early in the initial design, testingbecomes a major issue and ECOs are generated. In some extreme cases, are-spin is required to address the issue because ECOs may not work.

Cooling, Heat Sinks, and CTE
Coolingmethodologies are easily overlooked in a design, but taking care toassess cooling requirements early in the design can avoid ECOs.

Sometypes of cooling are water-based. For example, a huge specializedcomputer board with lots of BGAs and µPs for data intensive applicationslike animation and image or video manipulation most likely requires awater-based coolant.

When it comes to heat sinks, the PCB orheat-producing components are often connected to the chassis todissipate heat in the ambient. Other times, a heat sink, like the oneshown in Figure 6, is essential to help dissipate heat. If the rightheat sink isn’t specified, then an ECO is created. That ECO has to bedeveloped and introduced so that the heat sink can successfullydissipate the heat.

Figure 6: Heat sinks like this one are essential to help dissipate an inordinate amount of heat some components generate.

ThePCB designer needs to assure that components are thermally matched forcoefficient of thermal expansion (CTE) and that all associatedcalculations are incorporated. He or she makes doubly sure componentsare matched not only between components and their package sizes, butalso with PCB materials like FR4, Rogers, or Teflon to avoid creation ofan inordinate amount of heat or CTE differential between the componentsand the board. This assurance prevents de-lamination, which creates adefective device or maintains a large amount of electrical temperaturethat causes component or PCB burnout.

Zulki Khan isthe Founder and President of NexLogic Technologies, Inc. Prior toNexLogic, he was General Manager for Imagineering, Inc., Schaumburg,IL. He has also worked on high-speed PCB designs with signal integrityanalysis. He holds a B.S.E.E from N.E.D University and an M.B.A fromUniversity of Iowa and is a frequent author of contributed articles toEMS industry publications.

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