Siemens Digital Industries has added four new products in its Veloce hardware-assisted verification system which it said offer a seamless approach to managing rapid verification of next generation system on chip (SoC) designs. The complete system comprises virtual verification platform, hardware emulation and field programmable gate array (FPGA) prototyping, which together streamline and optimize verification cycles and reduce verification costs.
The new products are:
- Veloce HYCON (HYbrid CONfigurable) for virtual platform/software-enabled verification, allowing complex hybrid emulation systems for SoC designs.
- Veloce Strato+, a capacity upgrade to the Veloce Strato hardware emulator, with a roadmap that scales up to 15 billion gates.
- Veloce Primo for enterprise-level FPGA prototyping, an internally developed enterprise prototyping solution.
- Veloce proFPGA for desktop FPGA prototyping, featuring a modular approach to capacity, to deliver scalability across a range of capacity requirements.
Siemens said this highly cohesive system sets a standard for the future direction of hardware-assisted verification methodologies. This approach emphasizes running market-specific, real-world workloads, frameworks, and benchmarks early in the verification cycle for power and performance analysis. This enables customer-built virtual SoC models early in the cycle and the integration to begin running real-world firmware and software on Veloce Strato+ for deep-visibility to the lowest level of hardware.
Customers can then move the same design to Veloce Primo to validate the software/hardware interfaces and execute application-level software while running closer to actual system speeds. To make this approach as efficient as possible, Veloce Strato+ and Veloce Primo use the same RTL, the same virtual verification environment, the same transactors and models to maximize the reuse of verification collateral, environment and test content. This is a necessary foundation for a seamless methodology.
“As we enter the new semiconductor mega-cycle, the era of software-centric SoC design requires a dramatic change in functional verification systems to address new requirements,” said Ravi Subramanian, senior vice president and general manager, Siemens EDA. “The introduction of the next-generation Veloce system that addresses these key new requirements is a direct result of the focused investment from Siemens to offer our customers a complete, integrated system with a clear roadmap for the next decade. With today’s announcement, we are establishing a new standard for a system that is capable of supporting the new verification requirements across a diverse set of industries-spanning computing and storage, AI/ML, 5G, networking, and automotive.”
Siemens said innovation in chip, system, and software design enables Veloce Strato+ to deliver to the capacity roadmap published in 2017 when the Veloce Strato platform was introduced. Based on its Crystal 3+ — a new, proprietary 2.5D chip — it increases system capacity by 1.5x over the previous Veloce Strato system. This enables Veloce Strato+ to lead in the emulation market with available capacity of 15 billion gates. This capacity, which is the largest effective capacity available today, is now in use at multiple Veloce Strato+ customers.
AMD said it utilizes the Veloce emulation platforms as part of its pre-silicon verification and validation solutions. It worked with Siemens to deploy the high capacity Veloce Strato+ system at AMD, and its second and third generation AMD EPYC processors were qualified for use with the Veloce Strato and Veloce Strato+ platforms. The Veloce Strato system is also expanding the list of qualified processors by adding the AMD EPYC 7003 series processor. These new processors are fully qualified to run with the Veloce Strato systems as run time hosts and co-model hosts.
Another company developing with the Veloce Strato platform is SiPearl, the French startup which is designing the high-performance, low-power microprocessor for the European exascale supercomputer. Earlier this month it announced it passed a decisive milestone for the launch of Rhea, its first generation of microprocessors, in 2022. SiPearl said that while Rhea’s design is progressing well and on track, it has been able to move into an accelerated simulation phase on the hardware emulation platform developed by Siemens. It said the platform enables SiPearl to accelerate the pre-silicon functional verification process in a virtual environment thus validating Rhea’s capabilities before it moves into production.
For FPGA prototyping, Siemens added Veloce Primo and Veloce proFPGA. The enterprise-level FPGA prototyping system, Veloce Primo scales up to 320 FPGAs and has a consistent working model with Veloce Strato in terms of software workloads, design models and front-end compilation technology. This alignment between emulation and prototyping contributes to reducing the cost of verification by leveraging the right tool for the task where the emulation and the prototyping work together as complementary solutions for a better outcome in the shortest cycle. Veloce Primo also supports both virtual (emulation offload) and in-circuit-emulation (ICE) use models for highest possible performance while maintaining accurate clock ratios in both modes.
Commenting on this, Arm’s senior director of design services, Tran Nguyen, said, “The Veloce Primo enterprise FPGA prototyping solution from Siemens helps Arm quickly resolve design issues and achieve verification objectives so that our ecosystem can deliver quality Arm-based SoCs to support the rapid pace of innovation.”
And at Xilinx, Hanneke Krekels, its senior director of core vertical markets, said, “Xilinx has a long-standing relationship with Siemens both as a customer and as a collaboration partner, and we’re excited to provide our recent and industry-leading Virtex UltraScale+ VU19P device enabling scalability and capacity to this new product offering.”
Veloce proFPGA brings a proven, world-class desktop platform to the Veloce hardware-assisted verification system (via an OEM agreement with Pro Design). With a modular approach to capacity, the Veloce proFPGA family of products delivers scalability across a range of capacity requirements – from 40M gates to 800M gates – based on high-end FPGAs including Intel Stratix 10 GX 10M and Virtex UltraScale+ VU19P device.
“The advanced technology found in the proFPGA family delivers many advantages for validating today’s AI/ML, 5G, and data center ASIC designs,” said Gunnar Scholl, CEO of Pro Design. “Our collective experience, insight and strategy for the FPGA desktop prototyping market is being recognized, and we are excited to accelerate market penetration in this space through the collaboration with Siemens.”
- New tool tackles layout vs schematic verification of early “dirty” designs
- Automating C test cases for embedded system verification
- Software tools migrate GPU code to FPGAs for AI applications
- Drag and drop with new software and IP for processor-based FPGA design
- Multicore systems, hypervisors, and multicore frameworks
- EU funds development of secure low power embedded processors