Editor’s Note: In this Product How-To design article, Rama Sai Krishna V. provides an up-to-date breakdown on the newly released USB 3.0 specification, detailing the different layers in the USB 3.0 architecture. Also addressed are the significant changes in the each layer (physical, link, protocol) from the USB 2.0 spec and new power management features. Using the Cypress EZ-USB FX3 peripheral controller, the author describes when and where such capabilities are needed.
The Universal Serial Bus (USB) was designed to standardize the connection of computer peripherals such as keyboards, mice, printers, pen drives, hard disks, and portable media players, both to communicate and to supply the power needed for them. USB is the most common connectivity solution for PCs and consumer devices today. Plug and play, easy to use, and simple to implement, USB continues to gain traction in new applications and market segments.
The first version of the specification, USB 1.0, was released in 1996 and defined two transfer speeds to address the different types of devices available at that time. 1.5 Mbps (low speed) is to address devices such as keyboards and joysticks; 12 Mbps (full speed) is to address devices such as disk drives. The USB 2.0 specification was released in 2000 and supports a maximum signaling rate of 480 Mbps (high speed), which is 40 times the signaling rate of full speed.
We have one more revision in the USB specification, USB 3.0, even though 480 Mbps meets the speed requirement of the most of the devices available in the market today. The USB 3.0 specification was released in 2008 and supports a maximum signaling rate of 5 Gbps (SuperSpeed), which is 10 times the signaling rate of high speed.
The question is what applications require the Super Speed signaling rate. If you look at the advances in imaging data and storage, high speed data rates are not sufficient to address these markets now. You need around 118 MBps to stream an uncompressed High Definition video (1080p @ 30fps). Also, now you can have a SD card of size up to 2 TB according to the latest SD card specification (v3.0), which is called an Extended Capacity SD Memory Card (SDXC). The clock frequency of this card can run up to 208 MHz, allowing data rates up to 104 MBps. USB 3.0 can address these markets without reservations. USB 3.0 is backward compatible with USB 2.0; for that matter, USB has always maintained backward compatibility with older specifications.
The rest of the article discusses USB 3.0 architecture and goes into detail about the different layers. It will also address the significant changes in each layer (Physical, Link, Protocol) from the USB 2.0 spec, as well as new power management features.
USB 3.0 architecture
The USB 3.0 architecture contains three different layers: named the physical layer, the link layer on top of the physical layer, and the protocol layer on top of the link layer.
Click on image to enlarge.
The physical layer refers to the PHY part of the port and the cable connecting the upstream downstream ports. USB 3.0 cables have separate shielded differential pairs of lines for transmitting and receiving data. These lines exist along with the USB 2.0 signals. Thus, a USB 3.0 cable contains a total of 9 pins, including the 4 pins which are part of USB 2.0 cable. The maximum length of a USB 3.0 cable is limited to 3 meters due to the high signaling rate that it supports.
As for the power distribution by the USB 3.0 host, 150mA is considered as the unit load. The USB 3.0 host supplies 1 unit load of current for unconfigured devices and 6 unit loads of current for configured devices.
The USB 3.0 host detects the device connection based on the receiver end termination, and the transmitter is responsible for doing this action. USB 3.0 uses spread spectrum clocking on its signaling. Spread spectrum clocking spreads the energy of the signal over a larger frequency band rather than concentrating it over a small frequency band at a high level. This helps to reduce EMI emissions. The USB 3.0 physical layer supports Low Frequency Periodic Signaling (LFPS) which is used to manage signal initiation and low power management on the bus to consume less power on an idle link.
The link layer is responsible for maintaining a reliable and robust communication channel between the host and device. The Link Training and Status State Machine (LTSSM) is the core of the USB 3.0 link layer and defines link connectivity and link power management states and transitions. LTSSM consists of 12 states:
- Four link power states for better power management:
- U0 – normal operational mode
- U1 – Link idle with fast exit (PLL remains on)
- U2 – Link idle with slow exit (PLL may be off)
- U3 – Suspend
- U1, U2, U3 have increasingly longer wakeup times than U0, and thus allow transmitters to go into increasingly deeper sleep.
- Four link initialization and training states (Rx.Detect, Polling, Recovery, Hot Reset).
- Two link test states (Loopback and Compliance Mode).
- SS.Inactive (link error state where USB 3.0 is non-operable).
- SS.Disabled (SuperSpeed bus is disabled and operates as USB 2.0 only).
Link commands are used to maintain the link flow control and to initiate the change in link power state.
The protocol layer defines the communication rules between a host and device. USB 2.0 transactions consist of 3 packets: token, data, and handshake. A transaction is initiated with the token packet and this is always from the host. Data packets deliver the payload data and can be sourced by the host or device. Handshake packets acknowledge the error-free receipt of data and are sent by the receiver of data. In the case of SuperSpeed, however, to save bandwidth the token is incorporated into the data packet for OUT transactions. The token is replaced by the handshake for IN transactions; i.e., an ACK packet acknowledges the previous data packet that has been sent and requests the next data packet.
USB 3.0 packets are routed to the specific device with the help of the route string in the packet header. USB 3.0 does not poll for the readiness of the devices. If a device responds with “NRDY” (Not Ready) to an IN Transaction Packet (TP) from the host, then the host stops talking to that device until the device sends the “ERDY” (ready) packet saying that now it is ready to transmit the data.
USB 3.0 supports transmitting data in bursts (multiple data packets) without receiving an acknowledgement. The protocol allows efficient bus utilization by concurrently transmitting and receiving over the bus. A transmitter (host or device) can burst multiple packets of data back-to-back while the receiver can transmit data acknowledgements without interrupting the burst of data packets. Also, the host may simultaneously schedule multiple OUT bursts to be active at the same time as IN bursts.
USB 3.0 has enhanced the bulk capabilities of USB 2.0 by adding a protocol called “Stream”. This allows you to accept multiple commands on a pipe from the host, and allows you to complete them out of order using the stream IDs.
Power management features are implemented at all layers:
- The physical layer supports remote wakeup signaling.
- The link layer supports low-power link state entry and exit with the help of the LTSSM and link commands.
- The protocol layer supports endpoint busy/ready notifications.
- Devices support functions suspend. If a device has multiple functions, then each function can be asked to sleep separately. Also, you can request the whole device to sleep.
- Hubs forward the downstream link power state to the host.
- Hosts supports ping/ping response messaging.
Power efficiency at the system level
Asynchronous endpoint busy/ready notifications When a host finds that the device is busy then the host will not send any traffic until the device explicitly says it is ready. The device will notify the host by sending the “ERDY” notification when it becomes free. This will save some power as the host is not polling the device continuously. Packets routed with the help of a route string eliminates broadcasting as is required in the case of USB 2.0. Devices can also initiate low power link states when they are idle.
Figure 2 shows the internal block diagram of the EZ-USB FX3 next-generation SuperSpeed USB 3.0 peripheral controller that enables developers to add USB 3.0 device functionality to any system. The EZ-USB FX3 has an integrated USB 3.0 and USB 2.0 physical layer (PHYs) along with a 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications.
The EZ-USB FX3 has a fully configurable, General Programmable Interface (GPIF II) that can interface with any processor, ASIC, or FPGA. The GPIF II supports 8-, 16-, and 32-bit parallel data buses and enables interface frequencies up to 100 MHz. The EZ-USB FX3 contains 512 KB of on-chip SRAM for code and data. It also provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S.
Designing a UVC HD web camera using FX3
In the UVC HD camera design shown in Figure 3, an image sensor is connected to the GPIF II of the FX3. The GPIF II reads the uncompressed HD data stream from the image sensor and then it passed this data to the PC over USB. An I2C hardware block in the FX3 chip is used to initialize/configure the image sensor present in this UVC camera design. The FX3 device enumerates as a UVC device on the PC. We don’t need a separate driver to use this design as UVC is a standard class.
The various signals associated with the image sensor interface are:
- FV – Frame Valid, indicates start and stop of a frame.
- LV – Line Valid, indicates start and stop of a line.
- PCLK – Pixel clock, clock for the synchronous interface.
- Data – 8- to 32-bit data lines for image data.
Figure 4 shows a snapshot of the interface between the FX3 and image sensor on a GPIF II designer tool, the use of which allows developers to configure the FX3 registers to interface with any type of image sensor.
In this UVC HD camera design, you need around 56 MBps data rate on the USB bus if you are streaming an uncompressed semi HD (720p @30fps, 8-bit depth) data stream. If you are going to stream an uncompressed HD (1080p @30fps, 8-bit depth) data stream, then we need around 118 MBps data rate on the USB bus. However, USB 2.0 device controllers cannot meet these data rates so a USB 3.0 controller (FX3) is required to match these data rate requirements.
Rama Sai Krishna Vakkantula holds an M.Tech in Systems and Control Engineering from IIT Bombay, India. He is currently working as an applications engineer on Cypress USB 3.0 peripherals.