How do you get from beach sand to microprocessors? Prof. Turley explains the process. In doing so, he reveals a few secrets.
“Where do microprocessors come from, Daddy?” That's an awkward question we all must answer at some stage in our careers. What mysterious process converts elemental silicon into elemental forces like Intel's Itanium or Motorola's PowerPC? Let us explore the wonder that is semiconductor creation.
“When a customer and a vendor love each other very much . . .” they make a commitment to produce new chips. It's a big commitment, too. New chips generally cost a few million dollars to design, but that's small beer compared to what it costs to build a new chip-making factory. Fabs or foundries, as they're called, cost upwards of $2 billion to build. You could buy a lot of cruise missiles for that kind of money or several small Caribbean republics (island not included).
The amortization sucks, too. That $2 billion foundry will be obsolete in less than five years, so you're looking at more than $1 million of depreciation every single day. Very little of that cost goes into the silicon itself. You're mostly paying for the exotic equipment inside, including the neat-o air conditioners in the clean room.
In the beginning
Silicon chips all start out with, well, silicon. It's one of Earth's basic immutable chemical elements (element 14 in the periodic table, for those keeping score at home) and is basically purified beach sand. We're not likely to run out of this resource anytime soon. Tell your in-laws, by the way, that silicon is not the same as silicone. Silicone makes good weather stripping, a lubricant for squeaky hinges, and a source of income for cosmetic surgeons. It's not good for making microprocessor chips.
Raw silicon is grown into crystal ingots, which look like giant silver bolognas. Then it's sliced into exceptionally thin wafers about 6 to 8 inches (200 to 300mm) across, depending on the diameter of the ingot. Wafer (and ingot) diameters are standardized so that anyone's wafers can be processed in anyone's fab. A 300mm wafer is about as big around as a dinner plate and large enough for about 500 average-size chips.
From this point on, everything else happens in the fab's fancy clean room. “Clean” understates the case; these rooms are astonishingly, unbelievably sanitary. The best clean rooms are 1,000 times more pure and unpolluted than a hospital operating room. Stainless steel is everywhere; the floors and ceiling are perforated to promote air circulation; horizontal surfaces are sloped to avoid trapping dust, and yellow lighting discourages growth of single-cell organisms.
Clean room workers wear the now-familiar bunny suits. Looking like astronauts, these people are fully encapsulated and learn to recognize coworkers by their eyes. Getting in or out of a bunny suit takes about 15 minutes and involves walking across sticky floor mats and through an air shower. Breaks need to be carefully planned.
Let's see what develops
If you're a photographer or develop film in your own darkroom you'll already be familiar with what comes next. Silicon chips are made the same way that black and white prints are made. The entire fab is basically an enormous one-hour photo lab. The silicon wafer is the photographic print paper and the chip design is the negative. Mass-producing chips involves exposing the same negative a few hundred times over the entire surface of the wafer. When the wafer's been completely covered with chip “prints,” you're done.
A whole lot of things make this process more complicated than it sounds. First off, silicon wafers aren't photosensitive, so simply exposing them to light doesn't do anything. The wafers have to be coated with photoresist, a chemical concoction that conducts electricity but is also sensitive to light. After the wafer is evenly coated with resistwhich itself is a tricky processyou can expose it by shining light through your chip's film “negative.” That casts a chip-shaped shadow and imprints one copy of the chip onto the resist-covered wafer. After you wash away the exposed resist using ultrapure water and some other chemicals you've made one layer of one chip.
The idea here is to build up a three-dimensional stack of silicon, metal, and insulators. Chips are wired in 3D, they're not flat. They appear flat to the naked eyeextraordinarily flat, in factbut they're actually more like layered wedding cakes. A low-cost 8-bit microcontroller might have 8 to 10 layers while an exotic Athlon or Itanium has more than 40. Each of these is called a mask step or mask layer, and they all have to be done in sequence, from bottom to top.
Which brings us to the next problem. Each chip design has multiple layers, each with its own film negative. These layers need to be exposed one after another onto the same piece of silicon, exactly lining up. If the registration isn't perfect the layers of silicon, metal, and insulation will blur and the chip won't work. Unfortunately, you won't know that until after the chip's done and tested, and by that time you've already spent the time and money. Those chips wind up as paperweights, tie tacks, and sparkly souvenirs.
Superman, we need you
The other problem is that the film is invisible. Really. The patterns on each layer of the negative are so small and so fine that they're invisiblenot just to the naked eye, but to anything. The features are literally smaller than the wavelength of visible light. Shining normal light through a film layer would be like aiming a spotlight at a spider web; it won't cast a shadow. No shadow, no developing photoresist.
X-ray vision comes to the rescue. Instead of using visible light, chip makers use X-rays, extreme ultraviolet light (EUV), or laserlike beams of electrons (e-beam) aimed at the film layers. Even these science fiction techniques only forestall the inevitable. Film features are vanishingly small and getting smaller. Some chip makers now rely on interference patterns, like Moir patterns, to “trick” the equipment into casting sharp shadows from blurry images.
How small are we talking? Current state-of-the-art processing can create 90-nanometer-thin lines in silicon. That's 0.09 microns (micrometers), or 0.0000035433 of an inch. It's also only about 300 atoms. We're talking really small. This is what's known as the “feature size,” and it describes the smallest feature that can be resolved or, in other words, the thinnest wire that you can make.
Features sizes shrink in discrete steps because only a few companies produce the breathtakingly expensive chip-making equipment. Before 90nm production the smallest reliable size was 130nm (0.13 micron), and before that, 180nm (0.18 micron). If you go back enough years, features were all bigger than a micron. Chip-making technology has improved by several orders of magnitude since the 1960s and shows no sign of letting up.
When people talk about a chip made in “point one-three” they're talking about the feature size (0.13 micron). When they talk about “200 millimeters” they're talking about the wafer size. There's no relationship between wafer size and feature size; you can make any size features on any size wafer. In practical terms, though, companies almost always use the largest wafers and the smallest features possible. Here's why.
Smaller features (finer lines) are a good thing because they make for smaller chips. Smaller chips run faster because the electricity has less distance to travel. More important, smaller chips mean more profit. And more profit is a good thing.
For an example, let's look at a 200mm silicon wafer, which has about 986cm2 of surface area. That's about the size of a salad plate. Let's say your chips are square (most are) and they measure 10mm on a sidethat's 100mm2 per chip. If the silicon wafer was also square you could fit 986 chips on your wafer. Alas, wafers are round so you can really only get about 279 chips on a wafer. But if you could reduce the size of your chip by just 10% to 90mm2 , you'll fit 312 chips on a wafer. That's 12% more chips on the same amount of silicon. Not a bad deal.
Realistically, shifting to the next-smaller feature size slashes the size of a chip by about half, doubling the number of chips produced per wafer. Smaller features also reduce power consumption and heat dissipation, so finer lines are a win all the way around. The only downside is cost. Outfitting your fab with the latest lithography equipment to make these fine lines is not an inexpensive proposition.
Expensive real estate
Because most of the cost of chip making is in the equipment, not the silicon, your profitability depends entirely on volume. It's fairly accurate to say that the first chip costs you $2 billion to make; all the chips after that are free. Once you've paid for the fab, the labor and materials are, uh, immaterial. That's why smaller chips don't cost less, per se. They cost less because they increase the volume of product your $2 billion factory can produce. Silicon is like real estate: you're not paying for the dirt. You're paying for the space.
Lather, rinse, repeat
So now we've made one chip on a big wafer; how do we make more? That's the job of a stepper, a machine that carefully moves the wafer side to side until it's been completely covered with images of our new chip. As we saw before, a few hundred images will fit on a typical wafer. A few dozen more will partially fit and overlap the edge of the wafer. That's okay; we'll cut them off and discard them later.
Why not just use one big piece of film to expose the entire wafer at once? The problem is focus. As any photographer knows, the bigger the picture the blurrier the image. That's why big-screen TVs don't look so great up close. Chip images need to be ultra sharp, so a blurry “mega mask” wouldn't cut it.
Technically, today's chips are already slightly blurry at the edges. High-end chip designs compensate for this by putting less-critical circuitry in the corners. Intel's old i960MX microprocessor was octagonal. It was so big its corners had to be cut off.
Bringing out the diamonds
Once all our chips are exposed, rinsed, and exposed again, it's time to cut them apart into, well, chips. Up until now, our entire wafer has been handled all at once. All the chips were given a quick test while still on the wafer to see if any of them work. If they don't, the entire wafer gets tossed. If they do, the chips get cut apart. Using a diamond-edged saw, the wafer is diced up into individual chips and the “silicon sawdust” gets vacuumed away to avoid contaminating the finished chips.
A chip that's been cut loose from its wafer is called a die, and several die together are also called die, not dice. There's no particularly good reason for this grammatical inconsistency.
After each chip is tested to see if it works, it's usually tested again to see how fast it runs. Surprisingly, a 500MHz processor and a 700MHz processor aren't really different chips. They're probably neighboring chips from the same wafer that happen to run at different speeds. Slight variations in chemistry, contamination, or the phase of the moon seemingly can affect a chip's speed. It's common for microprocessor companies to sort their chips into at least two or three speed grades. The fastest 10% get sold at a premium price, while the slowest ones go to the bargain basementor get called something else.
Chip makers commonly lie about a chip's features. Well, maybe not lie exactly, but omit certain facts. You see, embedded processors with different features or peripherals often aren't different chips at all. Vendors will produce a single silicon design but then package and market it as different chips. For example, one version might have two UARTs and Ethernet while another version has five UARTs and no Ethernet. Chances are, they're really the same chip. Sometimes the “missing” features are disabled with a laser or by blowing a fuse. Sometimes they're disabled with firmware. As often as not, they aren't disabled at all, but just aren't mentioned on the data sheet. Programmers have occasionally found “secret” peripherals that aren't connected and aren't mentioned in the manuals.
Production quality tends to improve over time, so faster chips will become more plentiful. Sometimes it's not in the vendor's best interest to let customers know that, however. Even if half of the mature parts run at the peak speed, the vendor might arbitrarily limit the number of fast chips to, say, 15% of its volume to maintain an air of exclusivity. Enterprising customers have discovered this and over-clock their parts to gain a speed advantage.
Most chips are no bigger than your fingernail yet they contain the power and performance of room-sized mainframes from yesteryear. Any smaller and they'd be cheaper than the plastic package they're housed in; any bigger and they'd give off enough heat to melt themselves. Current semiconductor features are only a few hundred atoms thick in places. Surely we must be approaching the end of the road. But it doesn't look that way; new developments in lithography, epitaxy, and molecular manipulation should keep this family tree growing for many generations to come.
Jim Turley is an independent analyst, columnist, and speaker specializing in microprocessors and semiconductor intellectual property. He was past editor of Microprocessor Report and Embedded Processor Watch . For a good time, write to .
Just wanted to say that this is an excellent article which reduces a very complex process to easily understandable plain English a true accomplishment.
Jim, I would point out that a mask step is not the same as a layer. Some processors will have as many as 12 to 15 masks just for the silicon, before any oxide or metal is added.
State of the art processors from Intel (and, presumably, AMD) have 7 layers of metal (which, of course, implies at least 6 layers of dielectric). They probably run to your 40 or so mask steps.
Also, I would wonder at the observation that photoresists are electrical conductors. I know of none that are conductive when dry.
Ingot sizes are not typically “6 to 8 inches”, but are 6 or 8 or 12 (there are still a few ingots made, especially for analog processes and CCDs, that are smaller than 6 inches, but they are phasing out.)
I was very pleased to see your comments on the expense of a fab. Most gearheads aren't really aware of the impact of fab economics in this age, I'm afraid. Something else that adds to the cost is the cost of testing. Advanced DRAM testers depreciate at rates in excess of $100 per hour. And that goes straight to the cost basis of the chips that have to be tested.
All in all, a good and informative article, and one that should be read by young designers, so they can start to understand some of the economic forces they're dealing with. There are just these little things that an old anal-retentive type feels the need to pick at.
JL (Larry) McClellan
Author Jim Turley replies
You're correct about the difference between metal layers and mask steps. That's a simplification I made deliberately, based on an assumption about the readership. That was probably a bad call on my part, and one of the dangers of working in print. 😉
Ooops on the “6 to 8” inches; I meant 8 to 12, of course: 200 to 300 mm.
Just wanted to send you a note stating how much I enjoyed theEmbedded.com: Silicon 101 article. I have always wondered what the full sequence of events was but neverhad the time to try to find out. Thank you for an enjoyable 15 minutes of reading.
I can't believe you got through this whole article without once mentioning the processing steps deposition, etch, implant etc. You entirely missed the point of laying down the masks in the first place. The photoresist isn't conductive and isn't part of the chip – it's used as a mask to expose areas of silicon for chemical processing, and it's all stripped off before the next step.
I always thought that the silicon logs were treated with radiation before they were used. I know that a small nuclear plant here in Sweden “dopes” logs of silicon before use. I think it's called “neutron transmutation doped (NTD) silicon”; maybe this is only an experimental procedure. You can never be too sure though, semiconductors showed up just about the same time as nuclear power/bombs. Maybe someone tested a piece of sand from Trinity and found something beautiful! 🙂
I read your article on Embedded.com about silicon processing. I particularly enjoyed your relaxed and accessible style — a good mix of humor and solid technical content. It's always a delight to meet a fellow practitioner of good grammar and spelling, too. So rare amongst the technical crowd, that. I justwanted to say “well done”.
Senior Software Engineer
The PowerPC is not Motorola's processor. It's AIM's processor, and whose major contributor is IBM. AIM stands for Apple/IBM/Motorola. Apple brought in some of it's circuity design ingenuity and specifications, Motorola it's vector engine (AltiVec, which Apple calls Velocity Engine) and IBM, well, just about everything else, and the processor is mostly a spin-off of IBM's multi-chip Power 4 architecture.
Author Jim Turley replies
You're right that the PowerPC architecture belongs to IBM. Motorola uses it under license, and produces several PowerPC-compatible chips, all of which are now sold into embedded applications. Since I was writing for an audience of embedded programmers, I felt that readers would be more familiar with Motorola PowerPC chips rather than IBM PowerPC chips, which they might have never used.
I'm familiar AIM and Somerset, and I know some of PowerPC's designers personally. As I understand it, AltiVec is not part of the PowerPC architecture; that's Motorola property which IBM uses under license. Conversely, CodePack compression is IBM property, which Motorola might or might not someday use. And, as you say, PowerPC is based on, and is more or less compatible with, IBM's big Power processors.
I'd like to point out some mistakes in the article.
The yellow lights in a clean room are not to protect against biological threads. Instead they use a part of the light spectrum, which yields the least lithographic reaction on a not-yet developed wafer (just like a dark room is used when taking the film out of an ordinary old fashioned photo camera) to prevent uncontrolled development.
300mm, or pizza wafers, are not the same as 10-inch wafers. They are way more closer to 12 inch but in the industry they are referred to as 300mm, while the other sizes are called by their non-SI units like 4″, 5″, 6″ or 8″.
On your references to EUV and X-Ray: I'm not sure anybody uses them for production yet.
I just finished your Silicon 101 in Embedded Systems Programming magazine. I've covered the business side of the semiconductor and semiconductor equipment business for several years and this is the first intelligible explanation I've seen of the entire chip-making process. I've read a lot of articles that explain bits and pieces of the process wafers, feature size, etc. but your Silicon 101 puts all the pieces and steps together.
Thanks for a very useful article.
Jim ColeEast Bay Business TimesPleasanton CA
I found your article on the chip fabrication process very informative and well written. The only thing you touched on but didn't explain is why they can't make rectangular silicon wafers. I understand if it is too complicated for an e-mail response but it is the only thing that I felt wasn't fully addressed in the article.
Just thought I'd let you know I enjoyed your article on chip fabrication in this week's EEproductCenter. Well done!
D. W. Olmstead
I'm just sending this mail to thank you for your article Silicon 101, I really enjoyed it and am planning on forwarding it to some of the teachers in my school if that's fine by you and legal in my state (I'm not really informed on author's rights although I should because I write on a small publication in school). I study electronic engineering in ITESO University (Guadalajara, Mexico) and work on embedded systems development, so the article was also really informative because designers in my area aren't really acquainted with those things (especially in Mexico where not a lot of silicon level design takes place). Also, the way you write is quite fun. Anyway, thanks. Eduardo Viramontes Guerra
Ing. Electrnica, ITESO
Thanks you for the Silicon 101 article. I will share this with grade school children through our school's library and the science club. I am sure adults will appreciate it too. I am thinking about offering a prize for illustrations or scavenger-hunt examples of technology mentioned in the article. It could be a springboard for hands on science.
Sensor Research and Development Corporation (SRD Corp)
The photoresist does not remain on the chip to build layers, it is actually a temporary blocking layer that will block etching or doping of the underlying material. This underlying material may be silicon, polysilicon or metal (assuming a standard silicon process) that may be the original substrate or a deposited layer. Etching will remove any of the underlying material that is not protected (masked) by the photoresist. Doping will implant a material (p or n) into the unprotected (nonmasked) material. After the operation for this mask step is performed then the remaining photoresist is removed.
I've heard it said that when you can explain something to a child, you really understand the subject matter. You've really done this here. Even with my Semiconductors class in college, I still learned something in your article. It was very informative, and very readable. Thanks, and I'll pass this on to non-engineers as a great way to learn about how all those little µP's work…
I learned a lot, thank you, but there is a small inaccuracy in the article. When chips get smaller they get faster, not because light has less space to travel, but because (in a very general way) capacitiesget smaller quicker (quadratic) than the currents that charge them (resistances tend to keep their value but voltages are generally decreased by the chip maker for integrity issues), so they are charged quicker.
I have to admit though, that this is not an explanation for the general public.
Joao Santos Lima
Author Jim Turley replies
You're correct, of course. Capacitance is most of the reason for faster chips. But I felt that was too complicated for the general public, so I just said, “because it's shorter!”