SILICON ENGINEERING: System-in-package tools roll - Embedded.com

SILICON ENGINEERING: System-in-package tools roll

Santa Cruz, Calif. — Claiming to offer the first integrated suite of tools for system-in-package design, Cadence Design Systems Inc. this week will roll out an RF SiP Methodology Kit along with several additional tools for digital SiP design. Cadence will also announce a top-level, space-based router for mixed-signal and custom digital designs at 65 nanometers and below.

A SiP is a single package with two or more dice mounted together on a substrate. RF SiPs are becoming increasingly common for cell phone design, said Vishal Kapoor, group director for vertical-solutions marketing at Cadence, while digital SiPs may include stacked memories.

“This is the first set of dedicated SiP tools Cadence has offered,” said Keith Felton, product-marketing director for IC packaging and SiP solutions. “Nobody else has offered a complete solution, just bits and pieces.” Current solutions, he noted, typically lack the 3-D design tools that are needed to implement devices with stacked dice on top of a substrate.

Cadence's SiP tools offer that 3-D perspective, he said. Additionally, “We've integrated the SiP design into the standard RF full-custom IC environment supported by Virtuoso,” the company's custom IC design environment.

SiP RF Architect links into Virtuoso, and the SiP RF Layout tool provides a package substrate layout environment. Cadence does not yet offer an RF signal-integrity tool, so for now, the SiP Digital Signal Integrity (SI) tool is used in conjunction with third-party 3-D solvers.

SiP RF Architect and SiP RF Layout are part of Cadence's RF SiP Methodology Kit, which also includes “applicability consulting,” an 802.11 wireless-LAN reference design, pre- and postlayout simulation flows, a generic process design kit, an RF verification suite and comprehensive flow documentation. The consulting portion typically takes a week, Kapoor said.

The SiP RF Architect, Felton said, provides the “hooks and glue” needed to extend the Virtuoso schematic editor and Virtuoso Analog Design Environment (ADE) to SiP design. “Before, Virtuoso could not design multiple chips and connect them on a single substrate with a system-level connectivity view of the design,” he said. “That's what we've enabled.”

With the help of Architect, Virtuoso can provide footprints that are brought into the SiP RF Layout tool. That tool is a physical-layout editor that can implement a complete substrate design, Felton said. Users can also extract s-parameters that are fed back into the Virtuoso ADE for circuit simulation.

The RF kit will be available in the third quarter, with pricing starting at $50,000 for a one-year license.

The digital SiP solution includes SiP Digital Architect, SiP Digital Layout and SiP Digital SI. These tools are tied to Cadence's Encounter digital IC design system. Cadence does not, however, currently offer a methodology kit to digital designers.

SiP Digital Architect provides concept planning and feasibility analysis. A system connectivity manager provides a way to define and explore system connectivity and functionality, while optimizing among the ICs, the SiP substrate and the target pc board.

The SiP Digital Layout editor is a constraint- and rules-driven substrate layout environment that supports 3-D die stacking, I/O pad ring optimization and connectivity optimization. The SiP Digital SI product offers co-simulation of system interconnect including ICs, substrate interconnect and the target pcb. It includes 3-D parasitic extraction and modeling.

Custom routing
Cadence will also release its Precision Router this week. Integrated with the Virtuoso layout environment, this is a shape-based, full-chip routing solution for mixed-signal and custom digital chips at 65 nm and below. The first release provides only top-level routing, but Cadence promises detailed routing in the future.

Precision Router is a totally new product designed as part of Cadence's Catena technology incubation project, said Richard Brashears, corporate vice president for advanced technology development. Unlike the existing shape-based, top-level Cadence Chip Assembly Router, Brashears said, Precision Router simultaneously handles a “tiered” set of manufacturing and performance rules, providing a more robust constraint architecture. It also adds more speed and capacity for extremely complex designs, he said.

The router is completely interactive and also has batch algorithms for autorouting, Brashears said. Additionally, Precision Router claims an incremental capability that can make changes to extremely small areas of the design without affecting other areas. One key feature of the new router is an incremental electrical analysis. Wilbur Luo, an engineer in Cadence's advanced-technology development unit, noted that the router dynamically updates parasitics as the user is changing nets or manipulating shapes.

The router can dynamically change width and spacing, insert double vias, rotate vias or shift vias to eliminate edge corners that would complicate optical proximity correction.

The router is available now, and cost depends on configuration.

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